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* i965/nir: Make use of nir_opt_undefBoyan Ding2015-08-271-0/+2
| | | | | | | | | | | | Shader-db result on Ivy Bridge: total instructions in shared programs: 145484 -> 145445 (-0.03%) instructions in affected programs: 225 -> 186 (-17.33%) helped: 5 HURT: 0 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Thomas Helland <[email protected]> Signed-off-by: Boyan Ding <[email protected]>
* glapi: Remove _x86_64_get_get_dispatch symbol from x86-64 assembly.Matt Turner2015-08-271-6/+0
| | | | | | Never used. Reviewed-by: Mark Janes <[email protected]>
* glsl: clean up textureSize prototypeIlia Mirkin2015-08-271-4/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* r600g/sb: Don't crash on empty if jump targetGlenn Kennard2015-08-281-1/+4
| | | | | | Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: Don't read junk after EOPGlenn Kennard2015-08-283-1/+6
| | | | | | | | | | | | | Shaders that contain instruction data after an instruction with EOP could end up parsing that as an instruction, leading to various crashes and asserts in SB as it gets very confused if it sees for instance a loop start instruction jumping off to some random point. Add a couple of asserts, and print EOP bit if set in old asm printer. Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600g/sb: Handle undef in read port trackerGlenn Kennard2015-08-281-1/+1
| | | | | | | | | e8e443 missed adding check for undef values also in unreserve function, leading to an assert triggering. Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: rename rowStride to imageStride in texturesubimage()Brian Paul2015-08-271-4/+4
| | | | Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: only copy the requested teximage facesIlia Mirkin2015-08-271-2/+2
| | | | | | | | | | | | | | Cube maps are special in that they have separate teximages for each face. We handled that by copying the data to them separately, but in case zoffset != 0 or depth != 6 we would read off the end of the client array or modify the wrong images. zoffset/depth have already been verified by the time the code gets to this stage, so no need to double-check. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: "10.6 11.0" <[email protected]>
* nir: Convert the builder to use the new NIR cursor API.Kenneth Graunke2015-08-2711-61/+38
| | | | | | | | | | | | | | | | | | The NIR cursor API is exactly what we want for the builder's insertion point. This simplifies the API, the implementation, and is actually more flexible as well. This required a bit of reworking of TGSI->NIR's if/loop stack handling; we now store cursors instead of cf_node_lists, for better or worse. v2: Actually move the cursor in the after_instr case. v3: Take advantage of nir_instr_insert (suggested by Connor). v4: vc4 build fixes (thanks to Eric). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]> [v4] Acked-by: Connor Abbott <[email protected]> [v4]
* nir: Convert the NIR instruction insertion API to use cursors.Kenneth Graunke2015-08-272-97/+89
| | | | | | | | | | | | | | | | | This patch implements a general nir_instr_insert() function that takes a nir_cursor for the insertion point. It then reworks the existing API to simply be a wrapper around that for compatibility. This largely involves moving the existing code into a new function. Suggested by Connor Abbott. v2: Make the legacy functions static inline in nir.h (requested by Connor Abbott). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Connor Abbott <[email protected]>
* nir: Move nir_cursor to nir.h.Kenneth Graunke2015-08-272-89/+97
| | | | | | | | | | | We want to use this for normal instruction insertion too, not just control flow. Generally these functions are going to be extremely useful when working with NIR, so I want them to be widely available without having to include a separate file. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Connor Abbott <[email protected]>
* nir: Strengthen "no jumps" assertions in instruction insertion API.Kenneth Graunke2015-08-271-5/+5
| | | | | | | | | | | | | Jumps must be the last instruction in a block, so inserting another instruction after a jump is illegal. Previously, we only checked this when the new instruction being inserted was a jump. This is a red herring - inserting *any* kind of instruction after a jump is illegal. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Connor Abbott <[email protected]>
* st/mesa: use PROGRAM_ARRAY for storing structs containing arraysBrian Paul2015-08-271-3/+29
| | | | | | | | | | | | | | Previously, we used PROGRAM_ARRAY only for variables which were arrays or matrices. But if the variable is a structure containing an array or matrix, we need to use PROGRAM_ARRAY for that too. Before, we failed an assertion: state_tracker/st_glsl_to_tgsi.cpp:4900: Assertion `src_reg->file != PROGRAM_TEMPORARY' failed. when running the piglit test glsl-1.20/execution/fs-const-array-of-struct-of-array.shader_test Reviewed-by: Marek Olšák <[email protected]>
* glsl: fix comment typo: s/filed/field/Brian Paul2015-08-271-1/+1
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* gallium/util: fix code formatting in u_blitter.hBrian Paul2015-08-271-30/+25
| | | | Trivial.
* i965/fs: Split VGRFs after lowering pull constantsJason Ekstrand2015-08-271-2/+2
| | | | | | | | | | The split_virtual_grfs code doesn't properly rewrite reladdr so we need to make sure that any uniform indirects are lowered away first. This fixes the glsl-fs-uniform-indexed-by-swizzled-vec4.shader_test in piglit Cc: "10.6" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i964/fs: Refactor assign_constant_locationsJason Ekstrand2015-08-271-46/+40
| | | | | | | | | Now that all constant locations are assigned in a single function, we can refactor it a bit to unify things. In particular, we now handle pull_constant_loc and push_constant_loc more similarly and we only modify stage_prog_data->params[] in one place at the end of the function. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Rename INTEL_DEBUG=vec4vs to INTEL_DEBUG=vec4.Kenneth Graunke2015-08-271-1/+1
| | | | | | | | | | | | | | | driParseDebugString() doesn't have actual code to parse comma separated lists (or any other supported options?); instead it dumbly uses strstr(). This means that INTEL_DEBUG="vec4vs" will trigger both DEBUG_VEC4VS and DEBUG_VS, as "vs" is also a substring. We should probably improve the driconf parsing, but for now, just rename the option so it's usable in the meantime. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Kristian Høgsberg <[email protected]>
* mesa: enable enums for OES_texture_storage_multisample_2d_arrayTapani Pälli2015-08-273-5/+6
| | | | | | | | | v2: use _mesa_is_gles31(ctx) for verifying we are on ES 3.1, remove _es31 usage from get_hash_params.py Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: add support for OES_texture_storage_multisample_2d_arrayTapani Pälli2015-08-276-6/+13
| | | | | | | | | | | v2: use ARB_texture_multisample enable bit Patch adds extension enable bit and enables required keywords and builtin functions for the extension. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: Add extension enable for OES_texture_storage_multisample_2d_arrayTapani Pälli2015-08-271-0/+1
| | | | | | | | v2: use ARB_texture_multisample bit to enable extension Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glapi: add GL_OES_texture_storage_multisample_2d_array extensionTapani Pälli2015-08-271-0/+19
| | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Marta Lofstedt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* swrast: add a new macro, FETCH_COMPRESSEDNanley Chery2015-08-261-198/+41
| | | | | | | | | This patch creates a new macro, FETCH_COMPRESSED - similar in nature to the other FETCH_* macros. This reduces repetition in the code that deals with compressed textures. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa: return bool instead of GLboolean in compressedteximage_only_format()Nanley Chery2015-08-261-3/+3
| | | | | | | | | In agreement with the coding style, functions that aren't directly visible to the GL API should prefer the use of bool over GLboolean. Suggested-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965: refactor miptree alignment calculation codeNanley Chery2015-08-261-55/+30
| | | | | | | | | | | | Remove redundant checks and comments by grouping our calculations for align_w and align_h wherever possible. v2: reintroduce brw. don't include functional changes. don't adjust function parameters or create a new function. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965: change the meaning of cpp for compressed texturesNanley Chery2015-08-264-35/+15
| | | | | | | | | | | | | | | | | | | | An ASTC block takes up 16 bytes for all block width and height configurations. This size is not integrally divisible by all ASTC block widths. Therefore cpp is changed to mean bytes per block if the texture is compressed. Because the original definition was bytes per block divided by block width, all references to the mipmap width must be divided the block width. This keeps the address calculation formulas consistent. For example, the units for miptree_level x_offset and miptree total_width has changed from pixels to blocks. v2: reuse preexisting ALIGN_NPOT macro located in an i965 driver file. v3: move ALIGN_NPOT into seperate commit. simplify cpp assignment in copy_image_with_blitter(). update miptree width and offset variables in: intel_miptree_copy_slice(), intel_miptree_map_gtt(), and brw_miptree_layout_texture_3d(). Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965: correct mt->align_h for 2D textures on SkylakeNanley Chery2015-08-261-3/+8
| | | | | | | | | | | In agreement with commit 4ab8d59a23, vertical alignment values are equal to four times the block height on Gen9+. v2: add newlines to separate declarations, statments, and comments. Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965: use ALIGN_NPOT for setting ASTC mipmap layoutsNanley Chery2015-08-262-15/+15
| | | | | | | | | | ALIGN is changed to ALIGN_NPOT because alignment values are sometimes not powers of two when working with ASTC. v2: handle texture arrays and LDR-only systems. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/macros: move ALIGN_NPOT to macros.hNanley Chery2015-08-262-6/+10
| | | | | | | | | | | Aligning with a non-power-of-two number is a general task that can be used in various places. This commit is required for the next one. v2: add greater than 0 assertion (Anuj). convert the macro to a static inline function. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/macros: add power-of-two assertions for alignment macrosNanley Chery2015-08-262-3/+13
| | | | | | | | | | | | | ALIGN and ROUND_DOWN_TO both require that the alignment value passed into the macro be a power of two in the comments. Using software assertions verifies this to be the case. v2: use static inline functions instead of gcc-specific statement expressions (Brian). v3: fix indendation (Brian). v4: add greater than zero requirement (Anuj). Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965/surface_formats: add support for 2D ASTC surface formatsNanley Chery2015-08-262-0/+119
| | | | | | | | | | | | | | | | | | Define two-thirds of the 2D Intel ASTC surface formats (LDR-only). This allows a 1-to-1 mapping from the mesa format to the Intel format. ASTC textures will default to being processed in LDR mode. If there is hardware support for HDR/Full mode and the texture is not sRGB, add the format bit necessary to process it in HDR/Full mode. v2: remove extra newlines. v3: follow existing coding style in translate_tex_format(). v4: expound on the GEN9_SURFACE_ASTC_HDR_FORMAT_BIT comment. update SF table - ASTC is actually supported in Gen8. v5: conform the ASTC MESA_FORMAT enums to the existing naming convention. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/teximage: return the base internal format of the ASTC formatsNanley Chery2015-08-261-0/+4
| | | | | | | | | | | | | | | | | This is necesary to initialize the gl_texture_image struct. From the KHR_texture_compression_astc_ldr spec: "Added to Section 3.8.6, Compressed Texture Images Add the tokens specified above to Table 3.16, Compressed Internal Formats. In all cases, the base internal format will be RGBA. The encoding allows images to be encoded with fewer channels, but this is always presented as RGBA to the sampler." v2. use _mesa_is_astc_format(). Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/teximage: accept ASTC formats for 3D texture specificationNanley Chery2015-08-261-7/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ASTC spec was revised as follows: Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to commands accepting ASTC format tokens in the New Tokens section [...]. Support only exists in the HDR submode: Add a second new column "3D Tex." which is empty for all non-ASTC formats. If only the LDR profile is supported by the implementation, this column is also empty for all ASTC formats. If both the LDR and HDR profiles are supported only, this column is checked for all ASTC formats. LDR-only systems should generate an INVALID_OPERATION error when attempting to call CompressedTexImage3D with the TEXTURE_3D target. v2. return the proper error for LDR-only systems. v3. update is_astc_format(). v4. use _mesa_is_astc_format(). v5. place logic in _mesa_target_can_be_compressed. v6. fix issues handling ASTC formats. Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/texcompress: enable translation between MESA and GL ASTC formatsNanley Chery2015-08-261-0/+114
| | | | | | | v3. conform the ASTC MESA_FORMAT enums to the existing naming convention. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/glformats: recognize ASTC formats as compressedNanley Chery2015-08-261-0/+29
| | | | | Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa: add ASTC extensions to the extensions tableNanley Chery2015-08-262-0/+4
| | | | | | | | v2: alphabetize the extensions. remove OES ASTC extension. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa: don't enable online compression for ASTC formatsNanley Chery2015-08-265-4/+80
| | | | | | | | | | | | | In agreement with the ASTC spec, this makes calls to TexImage*D unsuccessful. Implied by the spec, Generate[Texture]Mipmap and [Copy]Tex[Sub]Image*D calls must be unsuccessful as well. v2. actually force attempts to compress online to fail. v3. indentation (Matt). v4. update copytexture_error_check to account for CopyTexImage*D (Chad). Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* glapi: add support for KHR_texture_compression_astc_ldrNanley Chery2015-08-263-1/+42
| | | | | | | | v2: correct the spelling of the sRGB variants. remove spaces around "=" when setting the enum value. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/formats: define the 2D ASTC formatsNanley Chery2015-08-265-1/+139
| | | | | | | | | | | | | Define the mesa formats and make changes necessary for compilation without errors. Also add support for _mesa_get_srgb_format_linear(). v2. conform the ASTC MESA_FORMAT enums to the existing naming convention. v3. remove ASTC cases for _mesa_get_uncompressed_format(). This function is only used for generating mipmaps - something ASTC formats do not support due to lack of online compression. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* nouveau: avoid build failures since 0fc21ecfIlia Mirkin2015-08-263-3/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallium/radeon: read_registers should return bool meaning success or failureMarek Olšák2015-08-264-8/+10
| | | | | Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: add IB parser support for CP DMA packetsMarek Olšák2015-08-264-61/+122
| | | | | | | | | If the packet encoding is defined in the same format as register definitions, the python script can process them automatically and the parser support becomes trivial. Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: add IB tracing support for debug contextsMarek Olšák2015-08-265-16/+105
| | | | | | | | | This adds trace points to all IBs and the parser prints them and also prints which trace points were reached (executed) by the CP. This can help pinpoint a problematic packet, draw call, etc. Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: remove old CS tracing codeMarek Olšák2015-08-265-47/+3
| | | | | | | Some of it is left there and it will be re-used in the next commit. Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: parse and dump status registers on GPU hangMarek Olšák2015-08-261-0/+52
| | | | | | | | | | GPU hang detection must be enabled by setting: GALLIUM_DDEBUG=[timeout in ms] This may print too much information that we might not understand yet, but some of the bits are very useful. Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: add an IB parserMarek Olšák2015-08-261-0/+245
| | | | | Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: save the contents of indirect buffers for debug contextsMarek Olšák2015-08-263-0/+15
| | | | | | | This will be used by the IB parser. Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: generate register and packet tables for an IB parser from sid.hMarek Olšák2015-08-264-0/+190
| | | | | | | | | | | This makes writing a good IB parser a lot easier. It generates 2 tables: - packet3 table - register table with all registers, fields, and named values Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* radeonsi: remove duplicated register definitions and instruction definitionsMarek Olšák2015-08-261-3160/+0
| | | | | | | | | Instruction encoding isn't needed in Mesa. The border color address registers were duplicated. Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
* r600g,radeonsi: remove unused ill-formed register field definitionsMarek Olšák2015-08-262-2/+0
| | | | | Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
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