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* i965: Account for TES in is_drawing_points().Kenneth Graunke2016-03-181-1/+8
* nv50: Mark compute states as dirty on context switchPierre Moreau2016-03-191-0/+1
* nv50/ir: print SUBFM subopsSamuel Pitoiset2016-03-191-0/+9
* nv50: add a new validation path for computeSamuel Pitoiset2016-03-191-12/+13
* nv50: rework nv50_compute_validate_program()Samuel Pitoiset2016-03-193-31/+17
* nv50: rework the validation path for 3DSamuel Pitoiset2016-03-194-16/+36
* nv50: rename 3d binding points to NV50_BIND_3D_XXXSamuel Pitoiset2016-03-198-46/+46
* nv50: rename 3d dirty flags to NV50_NEW_3D_XXXSamuel Pitoiset2016-03-198-112/+112
* nv50: rename NV50_COMPUTE to NV50_CPSamuel Pitoiset2016-03-193-52/+52
* nv50: rename nv50_context::dirty to nv50_context::dirty_3dSamuel Pitoiset2016-03-198-57/+57
* st/mesa: clean up st_translate_texture_target()Brian Paul2016-03-181-25/+44
* st/mesa: simplify drawpixels shader code with tgsi transform helper functionsBrian Paul2016-03-181-64/+18
* st/mesa: simplify bitmap shader code with tgsi transform helper functionsBrian Paul2016-03-181-37/+8
* tgsi: add tgsi_transform_op3_inst() functionBrian Paul2016-03-181-0/+34
* egl: support EGL_LARGEST_PBUFFER in eglCreatePbufferSurface(...)Daniel Czarnowski2016-03-183-1/+13
* gallium/swr: Cleaned up some context-resource managementGeorge Kyriazis2016-03-175-26/+27
* mesa: remove remaining tabs in prog_parameter.cTimothy Arceri2016-03-181-8/+8
* mesa: inline _mesa_add_unnamed_constant()Timothy Arceri2016-03-182-24/+6
* mesa: simplify and inline _mesa_lookup_parameter_index()Timothy Arceri2016-03-183-41/+18
* mesa: make _mesa_lookup_parameter_constant staticTimothy Arceri2016-03-182-100/+94
* mesa: remove unused functionTimothy Arceri2016-03-181-6/+0
* st/mesa: honour sized internal formats in st_choose_format (v2)Nicolai Hähnle2016-03-171-21/+6
* glsl: disable varying packing when its not safeTimothy Arceri2016-03-184-53/+180
* glsl: pass disable_varying_packing bool to the lowering passTimothy Arceri2016-03-183-15/+24
* radeonsi: fix Hyper-Z hangs on P2 configsMarek Olšák2016-03-171-2/+8
* r300g: add missing layer argument to rws->buffer_get_handle() callBrian Paul2016-03-171-1/+1
* radeon/winsys: add layer support for BO exportChristian König2016-03-174-0/+7
* radeon/winsys: add offset support for BO import/exportChristian König2016-03-175-18/+33
* gallium/winsys/drm: add layer to struct winsys_handleChristian König2016-03-171-0/+5
* gallium/winsys/drm: add offset to struct winsys_handleChristian König2016-03-176-0/+13
* nir: propagate bitsize information in nir_searchConnor Abbott2016-03-173-27/+247
* nir: add a bit_size parameter to nir_ssa_dest_initConnor Abbott2016-03-1728-76/+137
* nir: rename nir_const_value fields to include bitsize informationIago Toral Quiroga2016-03-1724-130/+130
* nir: update opcode definitions for different bit sizesConnor Abbott2016-03-177-158/+283
* nir: add nir_{src,dest}_bit_size() helpersConnor Abbott2016-03-171-0/+12
* nir: Add a bit_size to nir_register and nir_ssa_defJason Ekstrand2016-03-173-4/+46
* nir/types: add a function to get the bitsize of a base typeConnor Abbott2016-03-171-0/+21
* i965/nir: fix check to resolve booleans to work with sized nir_alu_typeSamuel Iglesias Gonsálvez2016-03-171-1/+1
* nir: Add explicitly sized typesJason Ekstrand2016-03-171-1/+28
* i965/nir: Lower nir compute shader shared variablesJordan Justen2016-03-173-0/+11
* nir: Lower shared var atomics during nir_lower_ioJordan Justen2016-03-171-2/+85
* nir: Add support for lowering load/stores of shared variablesJordan Justen2016-03-175-8/+32
* nir: Add atomic operations on variablesJordan Justen2016-03-171-0/+27
* nir: Add compute shader shared variable storage classJordan Justen2016-03-177-3/+26
* nir/print: Add space after shader_storage var modeJordan Justen2016-03-171-1/+1
* i965: Skip execution size adjustment for instructions of width 4Iago Toral Quiroga2016-03-171-1/+13
* i965/vec4/gen6: fix exec_size for MOV with a width of 4 in generate_gs_ff_sync()Samuel Iglesias Gonsalvez2016-03-171-1/+3
* i965/vec4/gen6: fix exec_size for instructions with destination width of 4Samuel Iglesias Gonsalvez2016-03-171-0/+6
* i965/vec4/gen6: fix exec_size for instructions with width of 4 in generate_gs...Samuel Iglesias Gonsalvez2016-03-171-0/+3
* i965/gs/gen6: fix execsize for instructions with width of 4 in gen6_sol_progr...Samuel Iglesias Gonsalvez2016-03-171-1/+10
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