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* meta: Delete the PBO texture upload/download pathJason Ekstrand2017-10-124-97/+0
* i965: Use blorp instead of meta for PBO pixel readsJason Ekstrand2017-10-121-9/+51
* i965: Use blorp instead of meta for PBO texture downloadsJason Ekstrand2017-10-121-4/+29
* i965/tex: Use blorp texture upload for all CCS_E texturesJason Ekstrand2017-10-121-1/+2
* i965: Use blorp instead of meta for PBO texture uploadsJason Ekstrand2017-10-121-4/+30
* i965: Add blorp-based texture upload and download pathsJason Ekstrand2017-10-122-0/+362
* i965: Refactor y-flipping coordinate transform.Kenneth Graunke2017-10-121-7/+11
* i965/tex: Check if there is data to upload up-frontJason Ekstrand2017-10-121-0/+4
* i965/barrier: Do the correct flushes for framebuffer accessJason Ekstrand2017-10-121-1/+1
* i965/barrier: Do the correct flushes for texture updatesJason Ekstrand2017-10-121-2/+4
* i965: Ignore GL_SKIP_DECODE_EXT for textures accessed via texelFetch().Kenneth Graunke2017-10-121-1/+5
* meta: Unset the textures_used_by_txf bitfield.Kenneth Graunke2017-10-121-0/+13
* nir: Make nir_shader_gather_info() track texelFetch texture accesses.Kenneth Graunke2017-10-121-1/+13
* compiler: Move gl_program::TexelFetchSamplers to shader_info.Kenneth Graunke2017-10-124-3/+6
* radv: take unsafe_math and sisched into account when hashing shaders.Dave Airlie2017-10-123-9/+24
* mesa/bufferobj: fix atomic offset/size getDave Airlie2017-10-131-2/+4
* mapi: Update extension number of MESA_tile_raster_order.Eric Anholt2017-10-121-2/+1
* broadcom/vc5: Remove the u_resource_vtbl usage.Eric Anholt2017-10-123-25/+18
* mesa: Disallow GL_RED/GL_RG with half-floats on GLES2.Eric Anholt2017-10-121-0/+4
* radeonsi: implement sync_file import/exportMarek Olšák2017-10-122-2/+79
* winsys/amdgpu: implement sync_file import/exportMarek Olšák2017-10-123-7/+138
* ac: add radeon_info::has_sync_filecros-mesa-17.2.3-vanillachadv/cros-mesa-17.2.3-vanillaMarek Olšák2017-10-123-0/+3
* broadcom/vc5: Don't pair VPMSETUP with other peripheral access.Eric Anholt2017-10-121-0/+3
* broadcom/vc5: Fix inclusion of FS flag bits in dumping the FS address.Eric Anholt2017-10-121-1/+1
* st/dri: implement __DRIimageExtension::validateUsage properlyMarek Olšák2017-10-121-8/+22
* gallium: add pipe_screen::check_resource_capabilityMarek Olšák2017-10-125-0/+74
* ac/surface: add ac_surface::is_displayableMarek Olšák2017-10-122-0/+13
* amd/addrlib: add Addr2IsValidDisplaySwizzleModeMarek Olšák2017-10-124-2/+58
* meson: fix typo in isltournier.elie2017-10-121-1/+1
* etnaviv: Do GC3000 resolve-in-place when possibleWladimir J. van der Laan2017-10-124-4/+25
* egl_haiku: drop haiku_egl_driver structEric Engestrom2017-10-121-20/+14
* egl: remove left over _EGLMain_tEric Engestrom2017-10-121-3/+0
* egl: drop memset(0) of calloc'ed memoryEric Engestrom2017-10-121-2/+0
* egl: replace _egl_driver->Unload() callback with a simple free()Eric Engestrom2017-10-124-28/+1
* radv: don't crash if cache is disabled.Dave Airlie2017-10-121-5/+9
* radv: use CLEAR_STATE for initializing some registersSamuel Pitoiset2017-10-121-41/+58
* radv: add has_clear_state and enable it on CIK+ onlySamuel Pitoiset2017-10-122-1/+6
* radv: do not set registers for merged ES-GS on GFX9Samuel Pitoiset2017-10-121-2/+5
* radv: move the raster config emission in si_set_raster_config()Samuel Pitoiset2017-10-121-53/+60
* radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORMNicolai Hähnle2017-10-121-0/+8
* gallium: add tests for PIPE_FORMAT_{X1,A1}B5G5R5_UNORM formatsNicolai Hähnle2017-10-121-0/+13
* radv: remove duplicate line of codeTimothy Arceri2017-10-121-1/+0
* radv: make use of on-disk cacheTimothy Arceri2017-10-121-2/+25
* radv: create on-disk shader cacheTimothy Arceri2017-10-123-0/+34
* radv: remove duplicate debug_flags fieldTimothy Arceri2017-10-129-17/+14
* anv: intel: use anv_image's computed size for importing a BOLionel Landwerlin2017-10-111-11/+15
* anv: bo_cache: allow importing a BO larger than neededLionel Landwerlin2017-10-111-1/+1
* st/glsl_to_tgsi: the second destination doesn't support relative addressingNicolai Hähnle2017-10-111-5/+2
* st/glsl_to_tgsi: fix DFRACEXP with only one destinationNicolai Hähnle2017-10-111-15/+23
* st/glsl_to_tgsi: fix indirect access to 64-bit integerNicolai Hähnle2017-10-111-1/+1
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