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* i965: Implement basic modifier image creationBen Widawsky2017-03-151-4/+34
* radeonsi: implement TGSI opcodes TEX_LZ and TXF_LZMarek Olšák2017-03-152-6/+16
* glsl_to_tgsi: use TEX_LZ and TXF_LZ when availableMarek Olšák2017-03-151-6/+20
* glsl_to_tgsi: remove a redundant statementMarek Olšák2017-03-151-2/+0
* gallium: add TGSI opcodes TEX_LZ and TXF_LZMarek Olšák2017-03-154-5/+39
* gallium: add PIPE_CAP_TGSI_TEX_TXF_LZMarek Olšák2017-03-1517-0/+18
* radeonsi: disable sinking common instructions down to the end blockSamuel Pitoiset2017-03-151-0/+11
* tgsi: add missing compute shader entry in tgsi_get_processor_name()Samuel Pitoiset2017-03-151-0/+2
* radeonsi: clean up tex_fetch_ptrs()Samuel Pitoiset2017-03-151-6/+4
* glx: don't expose systemTimeExtension for DRI2/DRI3/DRISWEmil Velikov2017-03-153-4/+0
* anv: do not open random render node(s)Emil Velikov2017-03-151-15/+38
* radv: do not open random render node(s)Emil Velikov2017-03-151-12/+36
* radv/winsys: use drmGetDevice2 APIEmil Velikov2017-03-151-2/+2
* winsys/amdgpu: use drmGetDevice2 APIEmil Velikov2017-03-151-2/+2
* loader: use drmGetDevice[s]2 APIEmil Velikov2017-03-151-3/+3
* util/sha1: drop _mesa_sha1_{update, format} return typeEmil Velikov2017-03-154-16/+14
* util/sha1: rework _mesa_sha1_{init,final}Emil Velikov2017-03-156-64/+44
* util/sha1: add non-typedef name for the SHA1_CTX structEmil Velikov2017-03-152-1/+4
* radv: Remove unused descriptor set field.Bas Nieuwenhuizen2017-03-151-1/+0
* r600: refactor binding code for attach buffer to CB.Dave Airlie2017-03-151-33/+78
* r600: refactor out CB setup.Dave Airlie2017-03-151-104/+143
* r600: refactor texture resource words setup code.Dave Airlie2017-03-151-88/+131
* r600: factor out the code to initialise a buffer resource.Dave Airlie2017-03-151-29/+51
* r600g: make framebuffer atom rely on dual src blend state.Dave Airlie2017-03-154-2/+7
* intel/debug: Add a common INTEL_DEBUG=nohiz optionJason Ekstrand2017-03-145-6/+4
* anv/image: Move handling of INTEL_VK_HIZJason Ekstrand2017-03-141-2/+2
* radv: trivial tidy upsTimothy Arceri2017-03-152-5/+2
* util/disk_cache: scale cache according to filesystem sizeAlan Swanson2017-03-151-3/+8
* util/disk_cache: actually enforce cache sizeAlan Swanson2017-03-152-4/+24
* util/disk_cache: use LRU eviction rather than random evictionAlan Swanson2017-03-151-43/+34
* util/disk_cache: don't fallback to an empty cache dir on evictTimothy Arceri2017-03-151-6/+27
* util/disk_cache: use a thread queue to write to shader cacheTimothy Arceri2017-03-152-13/+75
* util/disk_cache: add helpers for creating/destroying disk cache put jobsTimothy Arceri2017-03-151-0/+40
* util/disk_cache: add thread queue to disk cacheTimothy Arceri2017-03-151-1/+15
* radv/ac: workaround regression in llvm 4.0 releaseDave Airlie2017-03-151-1/+12
* radv/ac: gather4 cube workaround integerDave Airlie2017-03-151-1/+71
* radv: Set driver version to mesa version;Bas Nieuwenhuizen2017-03-151-1/+23
* radv: Increase api version to 1.0.42.Bas Nieuwenhuizen2017-03-151-1/+1
* util/vk: Add helpers for finding an extension structJason Ekstrand2017-03-151-0/+17
* radv: Flush before copying with PKT3_WRITE_DATA in CmdUpdateBufferAlex Smith2017-03-141-0/+2
* radv: Emit cache flushes before CP DMA.Bas Nieuwenhuizen2017-03-141-0/+3
* anv: Properly enumerate physical devices when none are presentJason Ekstrand2017-03-141-2/+5
* nir/constant_expressions: Refactor helper functionsJason Ekstrand2017-03-141-24/+27
* nir: Rework conversion opcodesJason Ekstrand2017-03-1422-308/+218
* i965/fs: Re-arrange conversion operationsJason Ekstrand2017-03-141-36/+31
* i965/vec4: Get rid of the type parameter from to/from_doubleJason Ekstrand2017-03-142-24/+15
* glsl/nir: Use nir_type_conversion_opJason Ekstrand2017-03-141-37/+32
* nir: Rewrite nir_type_conversion_opJason Ekstrand2017-03-141-63/+92
* nir: Add a get_nir_type_for_glsl_base_type helperJason Ekstrand2017-03-141-2/+8
* nir/validate: Rework ALU bit-size rule validationJason Ekstrand2017-03-141-32/+33
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