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* vc4: Drop the unused "stride" field of surfaces.Eric Anholt2015-06-161-1/+0
| | | | We're always looking at the slice anyway, when we would have needed it.
* vc4: Handle refcounting the exec BO like we do in the kernel.Eric Anholt2015-06-164-10/+34
| | | | | This reduces the diff to the kernel, and will be useful when I make the kernel allocate more BOs as part of validation.
* vc4: Use VC4_SET/GET_FIELD for some RCL packets.Eric Anholt2015-06-164-77/+89
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* vc4: Make symbolic values for packet sizes.Eric Anholt2015-06-164-57/+86
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* vc4: Use symbolic values in texture ptype validation.Eric Anholt2015-06-161-10/+13
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* vc4: Move vc4_packet.h to the kernel/ directory, since it's also shared.Eric Anholt2015-06-164-3/+3
| | | | I want to notice discrepancies when I diff -u between Mesa and the kernel.
* i965/gen9: Disable Mip Tail for YF/YS tiled surfacesAnuj Phogat2015-06-162-2/+11
| | | | | | | | | | | | | | | Disabling miptails fixed the buffer corruption happening in FBO which use YF/YS tiled renderbuffer or texture as color attachment. Spec recommends disabling mip tails only for non-mip-mapped surfaces. But, without disabling miptails I couldn't get correct data out of mipmapped YF/YS tiled surface. We need better understanding of miptails before start using them. For now this patch helps move things forward. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* i965/gen9: Set vertical and horizontal surface alignmentsAnuj Phogat2015-06-161-6/+26
| | | | | | | | | | Patch sets the alignments for texture and renderbuffer surfaces. V3: Make changes inside horizontal_alignment() and vertical_alignment() (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Use BRW_SURFACE_* in place of GL_TEXTURE_*Anuj Phogat2015-06-161-3/+3
| | | | | | | | Makes no functional changes in the code. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Rename use_linear_1d_layout() and make it globalAnuj Phogat2015-06-162-5/+9
| | | | | | | | | This function will be utilised in later patches. V2: Make both pointers constants (Topi) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen9: Set tiled resource mode in surface stateAnuj Phogat2015-06-162-0/+27
| | | | | | | | This patch sets the tiled resource mode for texture and renderbuffer surfaces. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* egl/dri2: implement platform_surfacelessHaixia Shi2015-06-167-1/+193
| | | | | | | | | | | | | | | | | | The surfaceless platform is for off-screen rendering only. Render node support is required. Only consider the render nodes. Do not use normal nodes as they require auth hooks. v3: change platform_null to platform_surfaceless v4: make libdrm required for surfaceless v5: remove modified include guards with defined(HAVE_SURFACELESS_PLATFORM) v6: use O_CLOEXEC for drm fd Signed-off-by: Haixia Shi <[email protected]> Signed-off-by: Zach Reizner <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965/vec4: Fix the source register for indexed samplersNeil Roberts2015-06-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously when setting up the sample instruction for an indirect sampler the vec4 backend was directly passing the pseudo opcode's src0. However vec4_visitor::visit(ir_texture *) doesn't set the texture operation's src0 -- it's left as BAD_FILE, which when translated into a brw_reg gives the null register. In brw_SAMPLE, gen6_resolve_implied_move() inserts a MOV from the inst->base_mrf and sets the src0 appropriately. The indirect sampler case did not have a call to gen6_resolve_implied_move(). The fs backend avoids this because the platforms that support dynamic indexing of samplers (IVB+) have been converted to not use the fake-MRF hack, and instead send from proper GRFs. This patch makes it call gen6_resolve_implied_move before setting up the indirect message. This is similar to what is done for constant sampler numbers in brw_SAMPLE. The Piglit tests for sampler array indexing didn't pick this up because they were using a texture with a solid colour so it didn't matter what texture coordinates were actually used. The tests have now been changed to be more thorough in this commit: http://cgit.freedesktop.org/piglit/commit/?id=4f9caf084eda7 With that patch the tests for gs and vs are currently failing on Ivybridge, but this patch fixes them. There are no other changes to a Piglit run on Ivybridge. On Skylake the gs tests were failing even without the Piglit patch because Skylake needs the source registers to work correctly in order to send a message header to select SIMD4x2 mode. (The explanation in the commit message is partially written by Matt Turner) Tested-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* st/mesa: improve assertions in vp/fp translationMarek Olšák2015-06-161-2/+4
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: don't rebind constant buffers after every state change if GS is activeMarek Olšák2015-06-161-9/+3
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: generalize sso stage interleaving checkChris Forbes2015-06-161-17/+38
| | | | | | | | For tessellation. v2: cleanup by Marek Olšák Reviewed-by: Brian Paul <[email protected]>
* mesa: remove unused variables from gl_programMarek Olšák2015-06-161-2/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* glsl: add ir reader support for ir_barrierChris Forbes2015-06-161-0/+15
| | | | | | Picked from the tessellation branch. Reviewed-by: Brian Paul <[email protected]>
* glsl: print locations of variablesMarek Olšák2015-06-161-2/+6
| | | | Reviewed-by: Brian Paul <[email protected]>
* Revert "glsl: remove restriction on unsized arrays in GLSL ES 3.10"Timothy Arceri2015-06-161-9/+1
| | | | | | | | | | | | This reverts commit adee54f8269c5e9f4fde91d19f0e465afc8f14d8. Further down in the GLSL ES 3.10 spec it say: "If an array is declared as the last member of a shader storage block and the size is not specified at compile-time, it is sized at run-time. In all other cases, arrays are sized only at compile-time." Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* mesa: set override_version per api version overrideTapani Pälli2015-06-161-14/+24
| | | | | | | | | | | Before 9b5e92f get_gl_override was called only once, but now it is called for multiple APIs (GLES2, GL), version needs to be set always. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90797 Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Martin Peres <[email protected]> Tested-by: Martin Peres <[email protected]>
* i965: Fix aligning to the block size in intel_miptree_copy_sliceNeil Roberts2015-06-161-2/+4
| | | | | | | | | | | | | | | | | | This function was trying to align the width and height to a multiple of the block size for compressed textures. It was using align_w/h as a shortcut to get the block size as up until Gen9 this always happens to match. However in Gen9+ the alignment values are expressed as multiples of the block size so in effect the alignment values are always 4 for compressed textures as that is the minimum value we can pick. This happened to work for most compressed formats because the block size is also 4, but for FXT1 this was breaking because it has a block width of 8. This fixes some Piglit tests testing FXT1 such as spec@3dfx_texture_compression_fxt1@fbo-generatemipmap-formats Reviewed-by: Nanley Chery <[email protected]>
* nv50,nvc0: clamp uniform size to 64kIlia Mirkin2015-06-152-4/+4
| | | | | | | | | | The state tracker will pass through requests from buggy applications which will have the buffer size larger than the max allowed (64k). Clamp the size to 64k so that we don't get errors when uploading the constbuf data. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* nvc0/ir: fix collection of first uses for texture barrier insertionIlia Mirkin2015-06-151-5/+11
| | | | | | | | | | | | | One of the places we have to insert texbars is in situations where the result of the tex gets overwritten by a different instruction (e.g. in a conditional statement). However in some situations it can actually appear as though the original tex itself is an overwriting instruction. This can naturally never really happen, so just ignore the tex instruction when it comes up. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90347 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* egl: Drop check for driver != NULL.Eric Anholt2015-06-151-1/+1
| | | | | | | | | | | | Back in 2013, a patch was added (with 2 reviewers!) at the end of the block to early exit the loop in this case, without noticing that the loop already did. I added another early exit case, again without noticing, but Rob caught me. Just drop the loop condition that apparently surprises most of us, instead of leaving the end of the loop conspicuously not exiting on success. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* gallium: Drop the gallium-specific Android sw winsys.Eric Anholt2015-06-153-346/+0
| | | | | | | This was part of gallium_egl, and we now have the normal libEGL Android winsys support to handle it. Reviewed-by: Emil Velikov <[email protected]>
* vc4: Add support for building on Android.Eric Anholt2015-06-154-0/+80
| | | | | | | | v2: Add a comment explaining why we link libmesa_glsl. Drop warning option from freedreno. Add vc4 to the documentation for BOARD_GPU_DRIVERS. Reviewed-by: Emil Velikov <[email protected]>
* gallium: Enable build of NIR support on Android.Eric Anholt2015-06-151-0/+3
| | | | | | v2: Add a comment explaining why we link libmesa_glsl. Reviewed-by: Emil Velikov <[email protected]>
* egl/dri2: Fix Android Lollipop build on ARM.Eric Anholt2015-06-151-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* meta: Abort texture upload if pixels == null and no pixel unpack buffer setAnuj Phogat2015-06-151-1/+2
| | | | | | | | | | in case of glTexImage{1,2,3}D(). Texture has already been allocated at this point and we have no data to upload. With out this patch, with create_pbo = true, we end up creating a temporary pbo and then uploading uninitialzed texture data. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Neil Roberts <[email protected]>
* meta: Abort meta path if ReadPixels need rgb to luminance conversionAnuj Phogat2015-06-151-0/+9
| | | | | | | | | After recent addition of pbo testing in piglit test getteximage-luminance, it fails on i965. This patch makes a sub test pass. Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Turn need_rgb_to_luminance_conversion() in to a global functionAnuj Phogat2015-06-152-5/+9
| | | | | | | | This will be used by _mesa_meta_pbo_GetTexSubImage() in a later patch. Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* mesa: Use helper function need_rgb_to_luminance_conversion()Anuj Phogat2015-06-151-7/+4
| | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Handle integer formats in need_rgb_to_luminance_conversion()Anuj Phogat2015-06-151-1/+4
| | | | | | | Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Use is_power_of_two() helper functionAnuj Phogat2015-06-151-3/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Check for miptree pitch alignment before using ↵Anuj Phogat2015-06-151-1/+3
| | | | | | | | | | intel_miptree_map_movntdqa() We have an assert() in intel_miptree_map_movntdqa() which expects the pitch to be 16 byte aligned. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Remove break after returnAnuj Phogat2015-06-151-3/+0
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* nv50/ir: OP_JOIN is a flow instructionJürgen Rühle2015-06-151-1/+1
| | | | | | | | | | | OP_JOIN instructions are assumed to be flow instructions and mercilessly casted to FlowInstruction. This patch fixes an instance where an OP_JOIN is created as a plain instruction. This can cause crashes in the ir printer. [imirkin: add ->fixed = 1] Reviewed-by: Ilia Mirkin <[email protected]>
* ilo: add ilo_state_raster_{line,poly}_stippleChia-I Wu2015-06-156-43/+138
| | | | Initialize hardware stipple states on bound instead of on emission.
* ilo: add ilo_state_sample_patternChia-I Wu2015-06-159-186/+225
| | | | | Move sample pattern initialization from ilo_render to ilo_state_sample_pattern.
* ilo: add 3DSTATE_AA_LINE_PARAMETERS to ilo_state_rasterChia-I Wu2015-06-154-10/+17
| | | | Utilize ilo_state_raster to avoid redundant state change.
* gallium/util: add util_last_bit64Marek Olšák2015-06-141-0/+19
| | | | | | This will be needed by radeonsi. Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: fix "tesselation" typoMarek Olšák2015-06-141-1/+1
| | | | Trivial.
* r600g: handle TGSI input/output array declarations correctlyMarek Olšák2015-06-142-87/+89
| | | | Most of this code could be removed if r600g used tgsi_shader_info.
* ilo: merge ilo_state_3d*.[ch] to ilo_state.[ch]Chia-I Wu2015-06-157-276/+179
| | | | | With most code replaced to ilo_state_*, what was left did not belong there anymore.
* ilo: add ilo_state_ps to ilo_shader_csoChia-I Wu2015-06-1513-481/+160
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* ilo: add ilo_state_{vs,hs,ds,gs} to ilo_shader_csoChia-I Wu2015-06-1515-499/+363
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* ilo: embed ilo_state_sbe in ilo_shaderChia-I Wu2015-06-1511-254/+169
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* ilo: embed ilo_state_vf in ilo_ve_stateChia-I Wu2015-06-1512-330/+146
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* ilo: embed ilo_state_urb in ilo_state_vectorChia-I Wu2015-06-159-350/+185
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