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* radeonsi: use local ws variable in si_need_dma_spaceMarek Olšák2019-02-061-9/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't leak an index buffer if draw_vbo failsMarek Olšák2019-02-061-3/+5
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: make allocator_zeroed_memory unmappable and use bigger buffersMarek Olšák2019-02-061-1/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: clear allocator_zeroed_memory with SDMAMarek Olšák2019-02-064-12/+9
| | | | | | | | so that it can be used in parallel IBs. This also removes the SO_FILLED_SIZE hack. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: initialize textures using DCC to black when possibleMarek Olšák2019-02-063-13/+63
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno: a2xx: fix fast clearJonathan Marek2019-02-061-1/+0
| | | | | | | Fixes: 912a9c8d Signed-off-by: Jonathan Marek <[email protected]> Cc: 19.0 <[email protected]>
* egl: use coherent variable namesEric Engestrom2019-02-0624-383/+383
| | | | | | | | | | | | | | | | | `EGLDisplay` variables (the opaque Khronos type) have mostly been consistently called `dpy`, as this is the name used in the Khronos specs. However, `_EGLDisplay` variables (our internal struct) have been randomly called `dpy` when there was no local variable clash with `EGLDisplay`s, and `disp` otherwise. Let's be consistent and use `dpy` for the Khronos type, and `disp` for our struct. Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Emil Velikov <[email protected]> Acked-by: Eric Anholt <[email protected]>
* v3d: Whitespace consistency fix.Eric Anholt2019-02-051-1/+1
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* v3d: Fix copy-propagation of input unpacks.Eric Anholt2019-02-055-35/+94
| | | | | | | | | | | | | | | | | I had a single function for "does this do float input unpacking" with two major flaws: It was missing the most common thing to try to copy propagate a f32 input nunpack to (the VFPACK to an FP16 render target) along with several other ALU ops, and also would try to propagate an f32 unpack into a VFMUL which only does f16 unpacks. instructions in affected programs: 659232 -> 655895 (-0.51%) uniforms in affected programs: 132613 -> 135336 (2.05%) and a couple of programs increase their thread counts. The uniforms hit appears to be a pattern in generated code of doing (-a >= a) comparisons, which when a is abs(b) can result in the abs instruction being copy propagated once but not fully DCEed.
* v3d: Fix input packing of .l for rounding/fdx/fdy.Eric Anholt2019-02-052-1/+2
| | | | | | Avoids a regression in dEQP-GLES3.functional.shaders.derivate.fwidth.texture.* once we start copy-propagating more input packs.
* v3d: Fix pack/unpack of VFPACK operand unpacks.Eric Anholt2019-02-052-1/+33
| | | | We want to be able to copy propagate our texture unpacks into the vfpack.
* v3d: Fix dumping of shaders with alpha test.Eric Anholt2019-02-051-1/+3
| | | | We were trying to print a NULL entry from the table.
* v3d: Store the actual mask of color buffers present in the key.Eric Anholt2019-02-053-14/+16
| | | | | | | If you only bound rt 1+, we'd still emit a write to the rt0 that isn't present (noticed while debugging an ext_framebuffer_multisample-alpha-to-coverage-no-draw-buffer-zero regression in another change).
* v3d: Fix precompile of FRAG_RESULT_DATA1 and higher outputs.Eric Anholt2019-02-051-1/+1
| | | | I was just leaving the other MRT targets than DATA0 out, by accident.
* st/nir: Use src/ relative include path for autotoolsKristian H. Kristensen2019-02-052-2/+4
| | | | | | Fixes: cdc53fa81cbeb80373eac33ef7695d9025caf14b Acked-by: Kenneth Graunke <[email protected]> Signed-off-by: Kristian H. Kristensen <[email protected]>
* gallium: Add a PIPE_CAP_NIR_COMPACT_ARRAYS capability bit.Kenneth Graunke2019-02-054-2/+8
| | | | | | | | | Iris would like to use compact arrays for tesslevels and clip/cull distances. radeonsi will likely want to switch to these at some point, since it'll be necessary for GL_ARB_gl_spirv support, but it's not ready for them just yet. Reviewed-by: Timothy Arceri <[email protected]>
* st/nir: Call nir_lower_clip_cull_distance_arrays().Kenneth Graunke2019-02-051-0/+1
| | | | | | | | | | | | Today, st always sets LowerCombinedClipCullDistance, causing the GLSL IR lowering to run, giving us vec4[2] arrays. I would like to disable this and instead run the NIR lowering so that we get compact float[] arrays instead. Calling the new pass is a noop if the GLSL IR pass has already run, so it's safe to call the pass unconditionally. Reviewed-by: Timothy Arceri <[email protected]>
* nir: Avoid splitting compact arrays into per-element variables.Kenneth Graunke2019-02-051-0/+4
| | | | | | | | | | | | | | Compact arrays are used for special variables like clip and cull distances, or tessellation levels. Drivers using compact arrays assume that these values will always be actual arrays. We don't want to turn a float[1] gl_CullDistance into a single float; that would confuse drivers. Today, i965 uses compact arrays, and Gallium drivers use nir_lower_io_arrays_to_elements, so we haven't had any overlap that would demonstrate the issue. Iris will use both. Reviewed-by: Timothy Arceri <[email protected]>
* nir: Avoid clip/cull distance lowering multiple times.Kenneth Graunke2019-02-051-2/+12
| | | | | | | | | A couple places in st/nir assume that cull distances have been lowered away, so it will need to call this lowering pass for drivers which opt out of the GLSL IR lowering. The Intel backend also calls this pass, for i965 and anv. We need to only do it once. Reviewed-by: Timothy Arceri <[email protected]>
* nir: Bail on clip/cull distance lowering if GLSL IR already did it.Kenneth Graunke2019-02-051-2/+2
| | | | | | | | | | | | | We have a GLSL IR pass to convert clip/cull distance float[] arrays into vec4[2] arrays. In ff281e6204, we attempted to skip this pass if the GLSL IR lowering had already run. But, that code was not quite right, as we forgot to strip away the per-vertex IO array layer for geometry and tessellation shader varyings. If the GLSL IR pass has run, the variables will not be marked as "compact". So we can simply check that and bail. Reviewed-by: Timothy Arceri <[email protected]>
* compiler: Mark clip/cull distance arrays as compact before lowering.Kenneth Graunke2019-02-052-0/+14
| | | | | | | | | | nir_lower_clip_cull_distance_arrays() marks the combined clip/cull distance array as compact. However, when translating in from GLSL or SPIR-V, we were not marking the original float[] arrays as compact. We should do so. That way, we can detect these corner cases properly. Reviewed-by: Timothy Arceri <[email protected]>
* nir: Record info->fs.pixel_center_integer in lower_system_valuesKenneth Graunke2019-02-052-5/+6
| | | | | | | | | | | | | | | | | | radeonsi uses a system value for gl_FragCoord rather than an input var. These get translated into load_frag_coord NIR intrinsics, which lose the pixel_center_integer and origin_upper_left decorations. To cope with this, Tim added a shader_info field for pixel_center_integer, and made glsl_to_nir set it accordingly. prog_to_nir also needs to handle these fragcoord conventions. Instead of duplicating the logic to set the info field, just move it to nir_lower_system_values so it'll happen regardless of who makes the NIR. (For what it's worth, we don't need an info flag for origin_upper_left, because radeonsi lowers origin conventions in nir_lower_wpos_ytransform before nir_lower_system_values destroys the variable and qualifiers.) Reviewed-by: Eric Anholt <[email protected]>
* program: Extend prog_to_nir handle system values.Kenneth Graunke2019-02-051-0/+30
| | | | | | | | | | | Some drivers, such as radeonsi, use a system value for gl_FragCoord rather than an input variable. In this case, our Mesa IR will have a PROGRAM_SYSTEM_VALUE register, which we need to translate. This makes prog_to_nir work for Gallium drivers which expose the PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL capability bit. Reviewed-by: Eric Anholt <[email protected]>
* program: Use u_bit_scan64 in prog_to_nir.Kenneth Graunke2019-02-051-7/+6
| | | | | | | We can simply iterate the bits rather than using util_last_bit and checking each one up until that point. Reviewed-by: Eric Anholt <[email protected]>
* st/mesa: Add NIR versions of the PBO upload/download shaders.Kenneth Graunke2019-02-051-2/+188
| | | | | | Acked-by: Marek Olšák <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]>
* st/mesa: Add a NIR version of the OES_draw_texture built-in shaders.Kenneth Graunke2019-02-051-7/+62
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]>
* st/mesa: Add NIR versions of the clear shaders.Kenneth Graunke2019-02-051-13/+67
| | | | | | | | | | | | We implement the basic VS and FS, as well as the VS that does layered clears by writing gl_Layer from the vertex shader. Drivers which need a geometry shader for writing layer continue falling back to TGSI, as I didn't need this and so didn't bother implementing it. (We certainly could, however, if people want to add it in the future.) Reviewed-by: Marek Olšák <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]>
* st/mesa: Add NIR versions of the drawpixels Z/stencil fragment shaders.Kenneth Graunke2019-02-051-21/+119
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]>
* st/mesa: Add a NIR version of the drawpixels/bitmap VS copy shader.Kenneth Graunke2019-02-051-8/+29
| | | | | | | | | This provides a native NIR version of the DrawPixels/Bitmap passthrough vertex shader. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]>
* st/nir: Make new helpers for constructing built-in NIR shaders.Kenneth Graunke2019-02-054-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | The state tracker generates several built-in shaders in order to perform scissored clears, upload/download PBOs, and so on. These are currently constructed using TGSI, using ureg and u_simple_shader. I want to have NIR versions of these shaders, for my Gallium driver that has a NIR backend but no TGSI support. To that end, we'll want a few helpers to help construct simple shaders. This patch adds two new helpers: - st_nir_finish_builtin_shader() takes a manually constructed NIR shader, applies lowering passes (like st_link_nir would do for GLSL), and constructs the pipe_shader_state. - st_nir_make_passthrough_shader() makes a simple passthrough shader, which copies inputs to outputs. This is similar to u_simple_shaders. v2: Set info->fs.untyped_color_outputs for vc4/v3d (thanks Eric!). Reviewed-by: Marek Olšák <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]>
* st/nir: Move varying setup code to a helper function.Kenneth Graunke2019-02-052-20/+29
| | | | | | | | I want to reuse this for built-in shaders. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Rob Clark <[email protected]> Tested-by: Eric Anholt <[email protected]>
* nir/deref: Drop zero ptr_as_array derefsJason Ekstrand2019-02-051-0/+21
| | | | | | They are effectively (&x)[0] or *&x which does nothing. Reviewed-by: Lionel Landwerlin <[email protected]>
* nir: Move V3D's "the shader was TGSI, ignore FS output types" flag to NIR.Eric Anholt2019-02-054-10/+24
| | | | | | | | | | | | | | Ken's rework of mesa/st builtins to NIR means that we'll have more NIR shaders with color output types that are mismatched with the render target types. Since this is behavior that GLSL doesn't require, add it as a shader_info option so the driver can know that it needs to ignore the FS output's base type in favor of the actual render target's. This prevents needing additional variants in several mesa/st paths (clear, pbo upload, pbo download), given that the driver already has to handle the variants for any TGSI being passed to it (from u_blitter, for example). Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: wire up the state_pool_padding testEmil Velikov2019-02-051-0/+5
| | | | | | | | | Cc: Jason Ekstrand <[email protected]> Fixes: 927ba12b53c ("anv/tests: Adding test for the state_pool padding.") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]><Paste> Reviewed-by: Dylan Baker <[email protected]>
* nvc0/ir: replace cvt instructions with add to improve shader performanceKarol Herbst2019-02-052-0/+64
| | | | | | | | | | | | | | | | | | | gives me an performance boost of 0.2% in pixmark_piano on my gk106, gm204 and gp107. reduces the amount of generated convert instructions by roughly 30% in shader-db. v2: only for 32 bit operations move some common code out of the switch handle OP_SAT with modifiers v3: only for registers and const memory rework if clauses merge isCvt into this patch v4: merge isCvt into its use Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* gallium-xlib: query MIT-SHM before using it.Bart Oldeman2019-02-051-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | When Mesa is compiled for gallium-xlib using e.g. ./configure --enable-glx=gallium-xlib --disable-dri --disable-gbm -disable-egl and is used by an X server (usually remotely via SSH X11 forwarding) that does not support MIT-SHM such as XMing or MobaXterm, OpenGL clients report error messages such as Xlib: extension "MIT-SHM" missing on display "localhost:11.0". ad infinitum. The reason is that the code in src/gallium/winsys/sw/xlib uses MIT-SHM without checking for its existence, unlike the code in src/glx/drisw_glx.c and src/mesa/drivers/x11/xm_api.c. I copied the same check using XQueryExtension, and tested with glxgears on MobaXterm. This issue was reported before here: https://lists.freedesktop.org/archives/mesa-users/2016-July/001183.html Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Cc: <[email protected]>
* swr/rast: update SWR rasterizer shader statsAlok Hota2019-02-0510-38/+204
| | | | | | Primarily refactoring internal stats types Reviewed-by: Bruce Cherniak <[email protected]>
* loader/dri3: Use strlen instead of sizeof for creating VRR property atomMichel Dänzer2019-02-051-1/+1
| | | | | | | | | | | sizeof counts the terminating null character as well, so that also contributed to the ID computed for the X11 atom. But the convention is for only the non-null characters to contribute to the atom ID. Fixes: 2e12fe425fe3 "loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property" Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: add missing vec opcodes in lower_bool_to_floatJonathan Marek2019-02-051-0/+6
| | | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: release references to image textures when a context is destroyedGert Wollny2019-02-053-0/+15
| | | | | | | | | | | | | When a texture is still bound as an image and the context it was bound in is destroyed but not the texture, then the texture will still hold the resource and will not be freed when it is finally destroyed. Hence, release these references when the context is destroyed. This leak was triggered by virglrenderer: https://gitlab.freedesktop.org/virgl/virglrenderer/issues/86 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: release tokens after creating the shader programGert Wollny2019-02-051-0/+2
| | | | | | | | | | | | | | | | | | | | ureg_get_tokens clears the reference to the tokens, and create_compute_state makes a copy, hence the tokens must be explicitely released. Fixes: Direct leak of 256 byte(s) in 1 object(s) allocated from: #0 0x7ff729cf3c60 in realloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdbc60) #1 0x7ff721b1240c in tokens_expand ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:234 #2 0x7ff721b1c9c0 in get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:257 #3 0x7ff721b1c9c0 in copy_instructions ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2040 #4 0x7ff721b1c9c0 in ureg_finalize ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2090 #5 0x7ff721b1e919 in ureg_get_tokens ../../samba/mesa/src/gallium/auxiliary/tgsi/tgsi_ureg.c:2167 #6 0x7ff721f8b35a in si_create_dma_compute_shader ../../samba/mesa/src/gallium/drivers/radeonsi/si_shaderlib_tgsi.c:219 #7 0x7ff722043ed9 in si_compute_do_clear_or_copy ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:156 #8 0x7ff7220448d3 in si_clear_buffer ../../samba/mesa/src/gallium/drivers/radeonsi/si_compute_blit.c:247 #9 0x7ff7220350e8 in vi_dcc_clear_level ../../samba/mesa/src/gallium/drivers/radeonsi/si_clear.c:274 Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* isl: assert that Gen8+ don't have bit6_swizzlingCaio Marcelo de Oliveira Filho2019-02-041-0/+3
| | | | | | | v2: Rewrite the condition to more clearly match the comment. (Jordan) Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: skip bit6 swizzle detection in Gen8+Caio Marcelo de Oliveira Filho2019-02-041-2/+14
| | | | | | | | It is always false on Gen8+. Also, move the variable definition near its use. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: skip bit6 swizzle detection in Gen8+Caio Marcelo de Oliveira Filho2019-02-041-0/+14
| | | | | | | It is always false on Gen8+. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: keep the phi order when splitting blocksCaio Marcelo de Oliveira Filho2019-02-041-3/+2
| | | | | | | | All things being equal is better to keep the original order. Since the new block is empty, push the phis in order to tail. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]>
* nv50,nvc0: add explicit settings for recent capsIlia Mirkin2019-02-042-0/+4
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: 19.0 <[email protected]>
* panfrost: Implement Midgard shader toolchainAlyssa Rosenzweig2019-02-0513-2/+6383
| | | | | | | | | | | | | | | This patch implements the free Midgard shader toolchain: the assembler, the disassembler, and the NIR-based compiler. The assembler is a standalone inaccessible Python script for reference purposes. The disassembler and the compiler are implemented in C, accessible via the standalone `midgard_compiler` binary. Later patches will use these interfaces from the driver for online compilation. Signed-off-by: Alyssa Rosenzweig <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Acked-by: Emil Velikov <[email protected]>
* panfrost: Initial stub for Panfrost driverAlyssa Rosenzweig2019-02-0525-1/+3239
| | | | | | | | | | | | | This patch adds an initial stub for the Gallium driver, containing simple screen functions and the majority of the driver headers but no actual functionality. It further adds the winsys glue for linking in this stub driver via kmsro on Rockchip/Amlogic boards. Signed-off-by: Alyssa Rosenzweig <[email protected]> Acked-by: Jason Ekstrand <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Eric Anholt <[email protected]> Acked-by: Emil Velikov <[email protected]>
* radeonsi: fix crashing performance counters (division by zero)Marek Olšák2019-02-041-1/+1
| | | | Fixes: e2b9329f17 "radeonsi: move remaining perfcounter code into si_perfcounter.c"
* radeonsi: handle render_condition_enable in si_compute_clear_render_targetMarek Olšák2019-02-043-3/+8
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