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* vc4: Allow RCL blits to the edge of the surface.Eric Anholt2015-12-081-2/+8
| | | | | | | The recent unaligned fix successfully prevented RCL blits that weren't aligned inside of the surface, but we also want to be able to do RCL blits for the whole surface when the width or height of the surface aren't aligned (we don't care what renders inside of the padding).
* vc4: Add disabled debug printf for describing blits.Eric Anholt2015-12-081-0/+10
| | | | I keep typing variants of this while debugging RCL blits for MSAA.
* vc4: Fix check for tile RCL blits with mismatched y.Eric Anholt2015-12-081-1/+1
| | | | | This was a typo in 3a508a0d94d020d9cd95f8882e9393d83ffac377 that didn't show up in testcases at that moment.
* vc4: Fix compiler warning from size_t change.Eric Anholt2015-12-081-1/+1
| | | | I missed this when bringing over the kernel changes.
* i965: Make uniform offsets be in terms of bytesJason Ekstrand2015-12-076-22/+49
| | | | | | | | | | This commit pushes makes uniform offsets be terms of bytes starting with nir_lower_io. They get converted to be in terms of vec4s or floats when we cram them in the UNIFORM register file but reladdr remains in terms of bytes all the way down to the point where we lower it to a pull constant load. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/nir_uniforms: Replace comps_per_unit with an is_scalar booleanJason Ekstrand2015-12-071-13/+15
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/nir: Remove unused indirect handlingJason Ekstrand2015-12-071-33/+11
| | | | | | | | | The one and only place where the FS backend allows reladdr is on uniforms. For locals, inputs, and outputs, we lower it away before the backend ever sees it. This commit gets rid of the dead indirect handling code. Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/state: Get rid of dword_pitch arguments to buffer functionsJason Ekstrand2015-12-076-38/+19
| | | | | Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-27/+7
| | | | | | Cc: "11.0" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92909 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use a stride of 1 and byte offsets for UBOsJason Ekstrand2015-12-073-16/+13
| | | | | Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vec4: Use byte offsets for UBO pulls on Sandy BridgeJason Ekstrand2015-12-073-10/+31
| | | | | | | | | | | Previously, the VS_OPCODE_PULL_CONSTANT_LOAD opcode operated on vec4-aligned byte offsets on Iron Lake and below and worked in terms of vec4 offsets on Sandy Bridge. On Ivy Bridge, we add a new *LOAD_GEN7 variant which works in terms of vec4s. We're about to change the GEN7 version to work in terms of bytes, so this is a nice unification. Cc: "11.0" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Fix texture views of 2d array surfacesBen Widawsky2015-12-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It is legal to have a texture view of a single layer from a 2D array texture; you can sample from it, or render to it. Intel hardware needs to be made aware when it is using a 2d array surface in the surface state. The texture view is just a 2d surface with the backing miptree actually being a 2d array surface. This caused the previous code would not set the right bit in the surface state since it wasn't considered an array texture. I spotted this early on in debug but brushed it off because it is clearly not needed on other platforms (since they all pass). I have no idea how this works properly on other platforms (I think gen7 introduced the bit in the state, but I am too lazy to check). As such, I have opted not to modify gen7, though I believe the current code is wrong there as well. Thanks to Chris for helping me debug this. v2: Just use the underlying mt's target type to make the array determination. This replaces a bug in the first patch which was incorrectly relying only on non-zero depth (not sure how that had no failures). (Ilia) Cc: Chris Forbes <[email protected]> Reported-by: Mark Janes <[email protected]> (Jenkins) References: https://www.opengl.org/registry/specs/ARB/texture_view.txt Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92609 Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* radeonsi: last_gfx_fence is a winsys fenceNicolai Hähnle2015-12-071-1/+1
| | | | | Cc: "11.1" <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nvc0/ir: fix up mul+add -> mad algebraic opt, enable for integersIlia Mirkin2015-12-073-12/+11
| | | | | | | For some reason this has been disabled for integers ever since codegen was merged, despite there being emission code for IMAD. Seems to work. Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: fix imad sat/hi flag emission for immediate argsIlia Mirkin2015-12-071-8/+3
| | | | | | | | According to nvdisasm both the immediate and non-imm cases use the same bits. Both of these flags are quite rarely set though. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* i965: Add brw_device_info::min_ds_entries field.Kenneth Graunke2015-12-072-0/+12
| | | | | | | | | | | | | | | | | | From the 3DSTATE_URB_DS documentation: "Project: IVB, HSW If Domain Shader Thread Dispatch is Enabled then the minimum number of handles that must be allocated is 10 URB entries." "Project: BDW+ If Domain Shader Thread Dispatch is Enabled then the minimum number of handles that must be allocated is 34 URB entries." When the HS is run in SINGLE_PATCH mode (the only mode we support today), there is no minimum for HS - it's just zero. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add state bits for tess stagesChris Forbes2015-12-074-2/+28
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add backend structures for tess stagesChris Forbes2015-12-076-0/+98
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Set core tessellation-related limitsChris Forbes2015-12-071-2/+6
| | | | | | Signed-off-by: Chris Forbes <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Request lowering of gl_TessLevel* from float[] to vec4s.Kenneth Graunke2015-12-071-0/+2
| | | | | Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Create new files for HS/DS/TE state upload code.Kenneth Graunke2015-12-0710-110/+271
| | | | | | | | | | | | | | | | For now, this just splits the existing code to disable these stages into separate atoms/files. We can then replace it with real code. v2: Bump the render atoms in this patch so it compiles (in my branch, I'd bumped it in an earlier patch). 61 seems to be the minimum that works, which doesn't match the old value + the number of atoms I added in this patch, so apparently we had some slop before. v3: Actually disable the DS unit on Gen8+. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> [v1] Reviewed-by: Matt Turner <[email protected]>
* gk104/ir: sampler doesn't matter for txfIlia Mirkin2015-12-071-1/+1
| | | | | | | | | | We actually leave the sampler unset for OP_TXF, which caused the GK104+ logic to treat some texel fetches as indirect. While this works, it's incredibly wasteful. This only happened when the texture was > 0 (since sampler remained == 0). Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* radeonsi: disable DCC on StoneyMarek Olšák2015-12-071-0/+4
| | | | | Cc: 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* winsys/amdgpu: addrlib - port a Fiji bug fixSonny Jiang2015-12-072-1/+46
| | | | | | | | | | Fiji: Fixed tiled resource failures Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> v2: fix a compile failure (typo) - Marek
* winsys/amdgpu: addrlib - port Checks mip 0 for czDispCompatibleSonny Jiang2015-12-072-2/+5
| | | | | | Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* winsys/amdgpu: addrlib - port fix error for workaround for 1D tilingSonny Jiang2015-12-071-1/+1
| | | | | | Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* st/va: disable MPEG4 by default v2Christian König2015-12-071-1/+9
| | | | | | | | | | | | The workarounds are too hacky to enable them by default and otherwise MPEG4 doesn't work reliably. v2: add docs/envvars.html, CC stable and fix typos Signed-off-by: Christian König <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (v1) Reviewed-by: Ilia Mirkin <[email protected]> (v1) Cc: "11.1.0" <[email protected]>
* st/va: move HEVC functions into separate file v2Christian König2015-12-074-168/+215
| | | | | | v2: actually copy all of it Signed-off-by: Christian König <[email protected]>
* mesa: remove _mesa_tex_target_is_arrayAlejandro Piñeiro2015-12-072-17/+0
| | | | | | | | | | | | _mesa_is_array_texture provides the same functionality and: 1. it returns bool instead of GLboolean 2. it's not related to the texture format (texformat.c) 3. the name's a little shorter v2: remove _mesa_tex_target_is_array instead (Brian Paul) Reviewed-by: Brian Paul <[email protected]>
* i965: use _mesa_is_array_texture instead of _mesa_tex_target_is_arrayAlejandro Piñeiro2015-12-072-2/+2
| | | | | | | | | Both methods provide the same functionality, so one would be removed. v2: use _mesa_is_array_texture and not the other way (Brian Paul) Reviewed-by: Brian Paul <[email protected]>
* gk110/ir: fix imul hi emission with limm argIlia Mirkin2015-12-071-2/+2
| | | | | | | The elemental demo hits this case. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]>
* svga: use the debug callback to report issues to the state trackerBrian Paul2015-12-076-0/+62
| | | | | | | | | | | | | | | Use the new debug callback hook to report conformance, performance and fallbacks to the state tracker. The state tracker, in turn can report this issues to the user via the GL_ARB_debug_output extension. More issues can be reported in the future; this is just a start. v2: remove conditionals around pipe_debug_message() calls since the check is now done in the macro itself. v3: remove unneeded dummy %s substitutions Acked-by: Ilia Mirkin <[email protected]>, Reviewed-by: José Fonseca <[email protected]>
* gallium/util: check callback pointers for non-null in pipe_debug_message()Brian Paul2015-12-071-3/+5
| | | | | | | | | So the callers don't have to do it. v2: also check cb!=NULL in the macro Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* i965: Add defines for gather push constantsAbdiel Janulgue2015-12-071-0/+19
| | | | | | | | | v2 (Francisco Jerez): - Rename HSW_GATHER_CONSTANTS_RESERVED to HSW_GATHER_POOL_ALLOC_MUST_BE_ONE. - Rename BRW_GATHER_* prefix to HSW_GATHER_CONSTANT_*. Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Abdiel Janulgue <[email protected]>
* mesa: move GLES checks for SSO input/output validationTimothy Arceri2015-12-071-22/+23
| | | | | | | | | This function is unfinished there is a bunch more validation rules that need to be applied here. We will still want to call it for desktop GL we just don't want to validate precision so move the ES check to reflect this. Reviewed-by: Tapani Pälli <[email protected]>
* mesa: move GL_INVALID_OPERATION error to rendering callTimothy Arceri2015-12-073-25/+15
| | | | | | | | The validation api doesn't trigger this error so just move it to the code called during rendering. Reviewed-by: Tapani Pälli <[email protected]> Cc: Kenneth Graunke <[email protected]>
* mesa: move pipeline input/output validation inside ↵Timothy Arceri2015-12-071-15/+15
| | | | | | | | | | | | _mesa_validate_program_pipeline() This allows validation to be done on rendering calls also. Fixes 3 dEQP-GLES31.functional.separate tests. Cc: "11.1" <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Cc: Kenneth Graunke <[email protected]>
* glsl: re-validate program pipeline after sampler changeTimothy Arceri2015-12-071-0/+4
| | | | | | | Cc: "11.1" <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> Cc: Kenneth Graunke <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=93180
* r600: apply SIMD workaround to cayman also.Dave Airlie2015-12-071-1/+8
| | | | | | | | | | | At last on ARUBA this is required to stop tessellation hanging in heaven. This removes one of the SIMDs from use by the HS/LS. Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: fix regression introduced with ring emit changes.Dave Airlie2015-12-071-1/+2
| | | | This was adding one after a CUT which broke end primitive
* r600: remove stale tessellation commentDave Airlie2015-12-071-1/+0
| | | | | | pointed out by Marek. Signed-off-by: Dave Airlie <[email protected]>
* r600: enable tessellation for evergreen/cayman (v2)Dave Airlie2015-12-071-1/+9
| | | | | | | | | | This enables tessellation for evergreen/cayman, This will need changes before committing depending on what hw works etc. working are CAYMAN/REDWOOD/BARTS/TURKS/SUMO/CAICOS v2: only enable on evergreen and above.
* r600g: reduce number of ps thread on caicosDave Airlie2015-12-071-1/+1
| | | | | | this allows tess apps to start Signed-off-by: Dave Airlie <[email protected]>
* r600g: adjust ls/hs thread counts for sumoDave Airlie2015-12-071-4/+4
| | | | | | these stop tess hangs here. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: enable nstack check for tess ctrl/eval shaders.Dave Airlie2015-12-071-1/+1
| | | | | | | This just makes sure they register at least one stack usage frame like vertex shaders. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: handle lds read operations.Dave Airlie2015-12-071-1/+21
| | | | | | | | | Reads from the queue shouldn't be merged for now read operations. Reads from the queue shouldn't be merged for now, or put in T slots. Signed-off-by: Dave Airlie <[email protected]>
* r600/asm: add LDS ops and barrier to the once per group restriction.Dave Airlie2015-12-071-1/+1
| | | | | | | LDS ops must be scheduled in X slot, and barrier should be on its own in a group. Signed-off-by: Dave Airlie <[email protected]>
* r600: move VGT_VTX_CNT_EN into shader stages atom.Dave Airlie2015-12-071-2/+2
| | | | | | This should be enabled for tessellation shaders as well. Signed-off-by: Dave Airlie <[email protected]>
* r600: enable tcs/tes dumping for R600_DUMP_SHADERS.Dave Airlie2015-12-071-1/+1
| | | | | | Trivial patch just to enable dumping more. Signed-off-by: Dave Airlie <[email protected]>
* r600: handle SIMD allocation issue with HS/LSDave Airlie2015-12-071-0/+5
| | | | | | | | | At least one SIMD must be kept away from the HS/LS stages in order to avoid a hw issue on evergreen/cayman. This patch implements this workaround. Signed-off-by: Dave Airlie <[email protected]>
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