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* mesa: replace LOGF, EXPF with logf, expfBrian Paul2015-02-244-12/+8
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: replace FREXPF, LDEXPF with frexpf, ldexpfBrian Paul2015-02-243-11/+9
| | | | | | Start getting rid of some imports.h macros. Use the c99 functions instead. Reviewed-by: Matt Turner <[email protected]>
* targets/libgl-xlib: add src/ include dir to fix buildBrian Paul2015-02-241-0/+1
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* swrast: fix a few release build warningsBrian Paul2015-02-242-0/+2
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* r600g,radeonsi: fix streamout after pipeline stats have been usedMarek Olšák2015-02-242-13/+1
| | | | | | | | | | | EVENT_TYPE_PIPELINESTAT_STOP disables streamout queries too. Luckily, pipeline stats are enabled by default, so we don't even have to emit EVENT_TYPE_PIPELINESTAT_START. Tested on Hawaii, Bonaire, Redwood, RV730. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: small cleanup around current_rast_primMarek Olšák2015-02-241-9/+6
| | | | | | | | - remove the last parameter of si_emit_rasterizer_prim_state - remove the last unused parameter of si_emit_draw_registers - use current_rast_prim in si_emit_draw_registers Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set current_rast_prim in the right placeMarek Olšák2015-02-241-1/+7
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: simplify obtaining a shader property in si_emit_clip_regsMarek Olšák2015-02-241-2/+1
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: only preload VertexID for the GS copy shaderMarek Olšák2015-02-241-4/+6
| | | | | | The copy shader doesn't use any other preloaded VGPRs. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: dump the shader key when dumping shadersMarek Olšák2015-02-241-0/+38
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: cleanup of hex literalsMarek Olšák2015-02-244-32/+32
| | | | | | | | 0x3F800000 -> fui(1.0) 0x00000000 -> 0 Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: set PA_SU_HARDWARE_SCREEN_OFFSET to 0Marek Olšák2015-02-241-0/+2
| | | | | | It was probably 0 already, but it doesn't hurt to set it. Reviewed-by: Michel Dänzer <[email protected]>
* st/mesa: cleanup st_translate_geometry_programMarek Olšák2015-02-241-102/+30
| | | | | | | | | Mostly dead code or code that didn't do anything. Computing gs_num_outputs at the end was also useless. It's already set correctly. Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: inline st_free_tokensMarek Olšák2015-02-243-17/+3
| | | | Reviewed-by: Dave Airlie <[email protected]>
* st/mesa: cleanup st_geometry_program structureMarek Olšák2015-02-243-74/+36
| | | | | | | It's full of unused variables and variables only used in st_translate_geometry_program. Reviewed-by: Dave Airlie <[email protected]>
* mesa: add a missing GS support check in GetActiveUniformBlockivMarek Olšák2015-02-241-0/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* r600g: Implement GL_ARB_draw_indirect for EG/CMGlenn Kennard2015-02-2410-35/+129
| | | | | | | | | | | | | | | | Requires Evergreen/Cayman and radeon kernel module 2.41.0 or newer. Expected piglit fails due to hardware limitations: * arb_draw_indirect-draw-arrays-prim-restart Restarts not applied for DrawArrays commands * arb_draw_indirect-vertexid Base vertex offset is not included in vertex id Marek: bump vgt_state num_dw by 3 (= space needed for one register write) Signed-off-by: Glenn Kennard <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* freedreno/a4xx: aniso filteringRob Clark2015-02-241-4/+6
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-02-245-5/+20
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add ARB_instanced_arrays supportRob Clark2015-02-242-5/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: handle index_bias (i.e. base_vertex)Rob Clark2015-02-241-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: add support for vertexid and instanceid sysvalsRob Clark2015-02-242-11/+24
| | | | | | ir3 bits of it already in place from a3xx patch.. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: pass number of instances to drawRob Clark2015-02-243-6/+7
| | | | | | | a4xx has it's own draw packet, so needs equivalent update to what a3xx already got. Signed-off-by: Rob Clark <[email protected]>
* st/omx/dec/h264: fix picture out-of-order with poc type 0 v2Leo Liu2015-02-241-0/+5
| | | | | | | | | | | | poc counter should be reset with IDR frame, otherwise there would be a re-order issue with frames before and after IDR v2: add commit message Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: "10.4 10.5" <[email protected]>
* clover: Set appropriate flag defaults on memory object creation.Francisco Jerez2015-02-241-8/+18
| | | | | | | | | | | According to the spec when no device access mode is specified clCreateBuffer and clCreateImage* should default to read/write, and clCreateSubBuffer should default to the parent's device access flags. clCreateSubBuffer is also required to inherit the host access and host pointer flags from the parent. Reviewed-and-tested-by: EdB <[email protected]>
* clover: Add CL_MEM_HOST_* flag checks.EdB2015-02-242-7/+34
| | | | | | | | | | | Those flags have been introduced in OpenCL 1.2. [ Francisco Jerez: Rebase. Throw CL_INVALID_VALUE from clCreateSubBuffer if the subbuffer drops access flags from its parent. Use single function taking the set of allowed host access flags to validate memory transfer operands. ] Reviewed-by: Francisco Jerez <[email protected]>
* clover: Factor out memory object flags validation to a helper function.Francisco Jerez2015-02-241-34/+32
| | | | | | | And define constants for commonly used subsets of flags to save some typing. Reviewed-and-tested-by: EdB <[email protected]>
* vc4: Update to current kernel sources.Eric Anholt2015-02-248-49/+93
| | | | | | New BO create and mmap ioctls are added. The submit ABI gains a flags argument, and the pointers are fixed at 64-bit. Shaders are now fixed at the start of their BOs.
* r600: Fix build after 984f3069370cd4a347cb38269d430b428385affdEric Anholt2015-02-241-1/+1
| | | | | Same as for the CLAMP macro, undef it before including a header file that tries to make fields with that name.
* st/nine: Mark end of non-void function unreachableTobias Klausmann2015-02-241-1/+1
| | | | | Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium: include util/macros.hTobias Klausmann2015-02-241-55/+2
| | | | | | | | The most common macros are defined there, no use to duplicate these Clean up the already redefinded macros Signed-off-by: Tobias Klausmann <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* driconf: Update Catalan translationAlex Henrie2015-02-241-18/+34
| | | | Signed-off-by: Alex Henrie <[email protected]>
* driconf: Update Spanish translationAlex Henrie2015-02-241-5/+21
| | | | Signed-off-by: Alex Henrie <[email protected]>
* mesa: Add missing error checks to GetProgramInfoLog, GetShaderInfoLog and ↵Eduardo Lima Mitev2015-02-241-6/+32
| | | | | | | | | | | GetProgramiv Fixes 3 dEQP tests: * dEQP-GLES3.functional.negative_api.state.get_program_info_log * dEQP-GLES3.functional.negative_api.state.get_shader_info_log * dEQP-GLES3.functional.negative_api.state.get_programiv Reviewed-by: Ian Romanick <[email protected]>
* i965: Fix non-AA wide line rendering with fractional line widthsIago Toral Quiroga2015-02-244-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | "(...)Let w be the width rounded to the nearest integer (...). If the line segment has endpoints given by (x0,y0) and (x1,y1) in window coordinates, the segment with endpoints (x0,y0-(w-1)/2) and (x1,y1-(w-1/2)) is rasterized, (...)" The hardware it not rounding the line width, so we should do it. Also, we should be careful not to go beyond the hardware limits for the line width after it gets rounded. Gen6-7 define a maximum line width slightly below 8.0, so we should advertise a maximum line width lower than 7.5 to make sure that 7.0 is the maximum integer line width that we can select. Since the line width granularity in these platforms is 0.125, we choose 7.375. Other platforms advertise rounded maximum line widths, so those are fine. Fixes the following 3 dEQP tests: dEQP-GLES3.functional.rasterization.primitives.lines_wide dEQP-GLES3.functional.rasterization.fbo.texture_2d.primitives.lines_wide dEQP-GLES3.functional.rasterization.fbo.rbo_singlesample.primitives.lines_wide Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Fix ctx->Texture.CubeMapSeamlessIago Toral Quiroga2015-02-241-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The intel driver code, and apparently all other Mesa drivers, call _mesa_initialize_context early in the CreateContext hook. That function will end up calling _mesa_init_texture which will do: ctx->Texture.CubeMapSeamless = _mesa_is_gles3(ctx); But this won't work at this point, since _mesa_is_gles3 requires ctx->Version to be set and that will not happen until late in the CreateContext hook, when _mesa_compute_version is called. We can't just move the call to _mesa_compute_version before _mesa_initialize_context since it needs that available extensions have been computed, which again requires other things to be initialized, etc. Instead, we enable seamless cube maps since GLES2, which should work for most implementations, and expect drivers that don't support this to disable it manually as part of their context initialization setup. Fixes the following 192 dEQP tests: dEQP-GLES3.functional.texture.filtering.cube.formats.* dEQP-GLES3.functional.texture.filtering.cube.sizes.* dEQP-GLES3.functional.texture.filtering.cube.combinations.* dEQP-GLES3.functional.texture.mipmap.cube.* dEQP-GLES3.functional.texture.vertex.cube.filtering.* dEQP-GLES3.functional.texture.vertex.cube.wrap.* dEQP-GLES3.functional.shaders.texture_functions.texturelod.samplercube_fixed_* Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Return error if BeginQuery is called with an existing object of ↵Eduardo Lima Mitev2015-02-241-0/+16
| | | | | | | | | | | | | | | | | | | different type Section 2.14 Asynchronous Queries, page 84 of the OpenGL ES 3.0.4 spec states: "BeginQuery generates an INVALID_OPERATION error if any of the following conditions hold: [...] id is the name of an existing query object whose type does not match target; [...] Similar wording exists in the OpenGL 4.5 spec, section 4.2. QUERY OBJECTS AND ASYNCHRONOUS QUERIES, page 43. Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.fragment.begin_query Reviewed-by: Ian Romanick <[email protected]>
* mesa: Return INVALID_OPERATION when querying a never bound Query objEduardo Lima Mitev2015-02-241-4/+4
| | | | | | | | | | | | | | | | | Section 2.14 Asynchronous Queries, page 84 of the OpenGL ES 3.0.4 states: "The command void GenQueries( sizei n, uint *ids ); returns n previously unused query object names in ids. These names are marked as used, for the purposes of GenQueries only, but no object is associated with them until the first time they are used by BeginQuery." This means that any attempt to use or query a Query object id before it has ever been bound by calling glBeginQuery, should be assume to be an invalid object. Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.state.get_query_objectuiv Reviewed-by: Ian Romanick <[email protected]>
* mesa: Add _mesa_is_array_texture helperIago Toral Quiroga2015-02-242-0/+25
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: Fix error validating args for TexSubImage3DEduardo Lima Mitev2015-02-241-2/+2
| | | | | | | | | | | | | The zoffset and depth values were not being considered when calling error_check_subtexture_dimensions(). Fixes 2 dEQP tests: * dEQP-GLES3.functional.negative_api.texture.texsubimage3d_neg_offset * dEQP-GLES3.functional.negative_api.texture.texsubimage3d_invalid_offset Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Cc: "10.4 10.5" <[email protected]>
* i965/blorp: round to nearest when converting float into integerSamuel Iglesias Gonsalvez2015-02-241-4/+7
| | | | | | | | | | | | | | | | | | | | Fixes: dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_linear dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_y_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_y_linear dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_y_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_dst_y_linear dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_x_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_x_linear dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_y_nearest dEQP-GLES3.functional.fbo.blit.rect.out_of_bounds_reverse_src_dst_y_linear No piglit regressions. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Perform program state upload outside of atom handlingCarl Worth2015-02-2310-84/+89
| | | | | | | | | | | | | | | | | | | | | | | | Across the board of the various generations, the intial few atoms in all of the atom lists are basically the same, (performing uploads for the various programs). The only difference is that prior to gen6 there's an ff_gs upload in place of the later gs upload. In this commit, instead of using the atom lists for this program state upload, we add a new function brw_upload_programs that calls into the per-stage upload functions which in turn check dirty bits and return immediately if nothing needs to be done. This commit is intended to have no functional change. The motivation is that future code, (such as the shader cache), wants to have a single function within which to perform various operations before and after program upload, (with some local variables holding state across the upload). It may be worth looking at whether some of the other functionality currently handled via atoms might also be more cleanly handled in a similar fashion. Reviewed-by: Kenneth Graunke <[email protected]>
* egl, wayland: RGB565 format support on Back-bufferVivek Kasireddy2015-02-231-3/+38
| | | | | | | | | | | | | | | | | | | | | | In current code, color format is always hardcoded to __DRI_IMAGE_FORMAT_ARGB8888 when buffer or DRI image is allocated in function calls, get_back_bo and dri2_get_buffers, regardless of current target's color format. This problem may leads to incorrect render pitch calculation, which eventually ends up with wrong offset of pixels in the frame buffer when the image is in different color format from dri surf's, especially with different bpp. (e.g. RGB565-16bpp) Attached code patch simply adds RGB565 and XRGB8888 cases to two functions noted above to resolve the issue. v2: added a case of XRGB8888, format and bpp selection is done via switch-case (not "if-else" anymore) Signed-off-by: Vivek Kasireddy <[email protected]> Signed-off-by: Dongwon Kim <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]> Cc: "10.5" <[email protected]>
* mesa: move math-related function into new c99_math.h fileBrian Paul2015-02-231-1/+1
| | | | | | | | | | | | The alternative would be to include math.h in c99_compat.h but that seems heavy-handed. This patch also replaces INLINE with inline in the c99 math function wrappers. Fixes MSVC build. Acked-by: Matt Turner <[email protected]>
* nir/gcm: Add some missing break statementsJason Ekstrand2015-02-231-0/+4
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir: Copy-propagate vecN operations that are actually movesJason Ekstrand2015-02-231-16/+29
| | | | | | | | | | | | | | | | | | | We were already do this for ALU operations but we haven't for non-ALU operations. This changes that. total NIR instructions in shared programs: 2039883 -> 2022338 (-0.86%) NIR instructions in affected programs: 1768850 -> 1751305 (-0.99%) helped: 14244 HURT: 124 total FS instructions in shared programs: 4083960 -> 4084036 (0.00%) FS instructions in affected programs: 7302 -> 7378 (1.04%) helped: 12 HURT: 51 Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* ra: Disable round-robin strategy for optimistically colorable nodes.Francisco Jerez2015-02-231-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The round-robin allocation strategy is expected to decrease the amount of false dependencies created by the register allocator and give the post-RA scheduling pass more freedom to move instructions around. On the other hand it has the disadvantage of increasing fragmentation and decreasing the number of equally-colored nearby nodes, what increases the likelihood of failure in presence of optimistically colorable nodes. This patch disables the round-robin strategy for optimistically colorable nodes. These typically arise in situations of high register pressure or for registers with large live intervals, in both cases the task of the instruction scheduler shouldn't be constrained excessively by the dense packing of those nodes, and a spill (or on Intel hardware a fall-back to SIMD8 mode) is invariably worse than a slightly less optimal scheduling. Shader-db results on the i965 driver: total instructions in shared programs: 5488539 -> 5488489 (-0.00%) instructions in affected programs: 1121 -> 1071 (-4.46%) helped: 1 HURT: 0 GAINED: 49 LOST: 5 v2: Re-enable round-robin already for the lowest one of the nodes pushed optimistically onto the sack (Connor). v3: Use UINT_MAX instead of ~0, open-code MIN2 (Jason, Connor). Reviewed-by: Connor Abbott <[email protected]>
* i965/fs: Fix lower_load_payload() not to use an incorrect half for ↵Francisco Jerez2015-02-231-0/+8
| | | | | | immediates and uniforms. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Fix lower_load_payload() to take into account non-zero reg_offset.Francisco Jerez2015-02-231-2/+2
| | | | | | | | Fixes metadata guess when instructions in the program specify a destination register with non-zero reg_offset and when the payload of a LOAD_PAYLOAD spans several registers. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Remove logic to keep track of MRF metadata in lower_load_payload().Francisco Jerez2015-02-231-26/+13
| | | | | | | MRFs cannot be read from anyway so they cannot possibly be a valid source of LOAD_PAYLOAD. Reviewed-by: Jason Ekstrand <[email protected]>
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