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* etnaviv: Add sampler TS supportWladimir J. van der Laan2017-11-153-6/+99
* etnaviv: Flush TS cache before changing TS configurationWladimir J. van der Laan2017-11-151-0/+5
* etnaviv: Add TS_SAMPLER formats to etnaviv_formatWladimir J. van der Laan2017-11-152-74/+91
* etnaviv: Check that resource has a valid TS in etna_resource_needs_flushWladimir J. van der Laan2017-11-152-1/+18
* etnaviv: rnndb updateWladimir J. van der Laan2017-11-156-9/+20
* radv: it isn't an error to not support a format or driverDave Airlie2017-11-162-2/+2
* i965: Drop some reserved space remnants.Kenneth Graunke2017-11-152-4/+1
* intel: Drop mtypes.h include from brw_compiler.h.Kenneth Graunke2017-11-151-1/+0
* i965: Fold ABO state upload code into the SSBO/UBO state upload code.Kenneth Graunke2017-11-1510-189/+16
* i965: Use nir_lower_atomics_to_ssbos and delete ABO compiler code.Kenneth Graunke2017-11-158-139/+8
* i965: Make a better helper function for UBO/SSBO/ABO surface handling.Kenneth Graunke2017-11-153-94/+37
* radv: add the vertex buffers BO to the list at bind timeSamuel Pitoiset2017-11-151-3/+3
* radv: replace vb_dirty with RADV_CMD_DIRTY_VERTEX_BUFFERSamuel Pitoiset2017-11-152-4/+5
* radv: drop radv_cmd_dirty_mask_t typedefSamuel Pitoiset2017-11-152-3/+2
* radv: use an unsigned 32-bit integer for radv_queue::family_indexSamuel Pitoiset2017-11-152-2/+2
* radv: do not add the image BO in radv_set_dcc_need_cmask_elim_pred()Samuel Pitoiset2017-11-151-2/+0
* radv: do not add the image BO in radv_set_color_clear_regs()Samuel Pitoiset2017-11-151-2/+0
* r600: set the number type correctly for float rts in cb setupRoland Scheidegger2017-11-152-2/+15
* r600: use ieee version of rsqRoland Scheidegger2017-11-151-5/+1
* r600: use ieee version of rcpRoland Scheidegger2017-11-151-6/+2
* r600: use DX10_CLAMP bit in shader setupRoland Scheidegger2017-11-152-0/+15
* r600: use min_dx10/max_dx10 instead of min/maxRoland Scheidegger2017-11-152-6/+9
* r600: fix cubemap arraysDave Airlie2017-11-151-9/+17
* freedreno/a5xx: small comment fixRob Clark2017-11-141-1/+1
* freedreno/a5xx: indirect draw supportRob Clark2017-11-142-1/+37
* freedreno/a5xx: split out helper for pipeline stallsRob Clark2017-11-142-6/+13
* freedreno: update generated headersRob Clark2017-11-146-16/+135
* gallium/radeon: disable the cache when nir backend enabledTimothy Arceri2017-11-151-0/+4
* st/glsl_to_tgsi: use tgsi_get_gl_varying_semantic() for gs/tes outputsTimothy Arceri2017-11-151-91/+5
* gallium/tgsi: add tess output supoort to tgsi_get_gl_varying_semantic()Timothy Arceri2017-11-151-0/+8
* st/glsl_to_tgsi: make use of tgsi_get_gl_varying_semantic()Timothy Arceri2017-11-151-71/+11
* gallium/tgsi: add prim id to tgsi_get_gl_varying_semantic()Timothy Arceri2017-11-151-0/+4
* i965: Make use of brw_load_register_imm32() helper functionAnuj Phogat2017-11-145-40/+19
* i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DWAnuj Phogat2017-11-142-5/+19
* i965: Program DWord Length in MI_FLUSH_DWAnuj Phogat2017-11-142-2/+2
* anv/gen10: Enable float blend optimizationAnuj Phogat2017-11-141-0/+12
* intel/genxml: Add Cache Mode SubSlice Register to gen10.xmlAnuj Phogat2017-11-141-0/+12
* anv/gen10: Implement WaSampleOffsetIZ workaroundAnuj Phogat2017-11-141-0/+61
* mesa/st: add missing copyright headers to memoryobjects filesAndres Rodriguez2017-11-142-0/+48
* mesa: minor tidy up for memory object error stringsAndres Rodriguez2017-11-141-16/+14
* broadcom/vc4: fix indentation in vc4_screen.cAndres Rodriguez2017-11-141-8/+8
* Revert "intel/fs: Use a pure vertical stride for large register strides"Matt Turner2017-11-141-13/+3
* i965/fs: Fix extract_i8/u8 to a 64-bit destinationMatt Turner2017-11-141-2/+23
* i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLKMatt Turner2017-11-141-4/+4
* swr/rast: Faster emulated simd16 permuteTim Rowley2017-11-141-23/+11
* swr/rast: Use gather instruction for i32gather_ps on simd16/avx512Tim Rowley2017-11-141-11/+1
* egl/wayland: Add a fallback when fourcc query isn't supportedDerek Foreman2017-11-141-2/+30
* radeonsi: remove has_cp_dma, has_streamout flags (v2)Marek Olšák2017-11-143-20/+2
* i965: implement (un)mapImageJulien Isorce2017-11-141-2/+63
* radv: force enable LLVM sisched for The Talos PrincipleSamuel Pitoiset2017-11-141-0/+20
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