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* mesa: create locked version of HashWalkTimothy Arceri2017-04-252-8/+31
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* genxml: Fix gen_pack_header.py crash when field type is invalid.Rafael Antognolli2017-04-241-2/+2
| | | | | | | | Just return earlier in that case. Also set prefix to an empty string, so we don't get to use it undefined. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Make BLEND_STATE command support variable length array.Rafael Antognolli2017-04-247-48/+74
| | | | | | | | | | | | | | | | | | | | | | | | We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Fix python crash when no dwords are found.Rafael Antognolli2017-04-241-5/+12
| | | | | | | | | | | | | | | If the 'dwords' dict is empty, max(dwords.keys()) throws an exception. This case could happen when we have an instruction that is only an array of other structs, with variable length. v2: - Add another clause for empty dwords and make it work with python 3 (Dylan) - Set the length to 0 if dwords is empty, and do not declare dw Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* genxml: Remove unused parameter.Rafael Antognolli2017-04-241-2/+2
| | | | | | | 'start' parameter from Group.emit_pack_function() is useless. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/aubinator: Correctly read variable length structs.Rafael Antognolli2017-04-243-6/+54
| | | | | | | | | | | | | | | | Before this commit, when a group with count="0" is found, only one field is added to the struct representing the instruction. This causes only one entry to be printed by aubinator, for variable length groups. With this commit we "detect" that there's a variable length group (count="0") and store the offset of the last entry added to the struct when reading the xml. When finally reading the aubdump file, we check the size of the group and whether we have variable number of elements, and in that case, reuse the last field to add the remaining elements. Signed-off-by: Rafael Antognolli <[email protected]> Tested-by: Jason Ekstrand <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* isl/format: Update the R16G16B16X16_FLOAT entryNanley Chery2017-04-241-1/+1
| | | | | | | | | | | The section of the PRM mentioned in the code comment above this table says that this format supports the render target write message. Internal documentation says that this format also supports alpha blending. As a side effect, this allows CCS_D buffers to be created for images with this format. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* anv/pass: Delete anv_pass::subpass_attachmentsNanley Chery2017-04-241-1/+0
| | | | | | | This field has no users. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* intel/fs: Take into account amount of data read in spilling cost heuristic.Francisco Jerez2017-04-241-1/+1
| | | | | | | | | | | | | | | | | | | Until now the spilling cost calculation was neglecting the amount of data read from the register during the spilling cost calculation. This caused it to make suboptimal decisions in some cases leading to higher memory bandwidth usage than necessary. Improves Unigine Heaven performance by ~4% on BDW, reversing an unintended FPS regression from my previous commit 147e71242ce539ff28e282f009c332818c35f5ac with n=12 and statistical significance 5%. In addition SynMark2 OglCSDof performance is improved by an additional ~5% on SKL, and a Kerbal Space Program apitrace around the Moho planet I can provide on request improves by ~20%. Cc: <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/fs: Use regs_written() in spilling cost heuristic for improved accuracy.Francisco Jerez2017-04-241-2/+1
| | | | | | | | | | This is what we use later on to compute the number of registers that will actually get spilled to memory, so it's more likely to match reality than the current open-coded approximation. Cc: <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/vec4: Use reads_accumulator_implicitly(), not MACH checks.Kenneth Graunke2017-04-241-4/+4
| | | | | | | | | Curro pointed out that I should not just check for MACH, but use the reads_accumulator_implicitly() helper, which would also prevent the same bug with MAC and SADA2 (if we ever decide to use them). Cc: [email protected] Reviewed-by: Francisco Jerez <[email protected]>
* android: radv/ac: Fix nir.h includeMauro Rossi2017-04-241-0/+2
| | | | | | | | | | | | | | Fixes following building errors due to missing include paths: external/mesa/src/amd/common/ac_shader_info.c:23:10: fatal error: 'nir/nir.h' file not found ^ external/mesa/src/compiler/nir/nir.h:48:10: fatal error: 'nir_opcodes.h' file not found ^ Fixes: 224cf29 "radv/ac: add initial pre-pass for shader info gathering" Acked-by: Dave Airlie <[email protected]> Acked-by: Emil Velikov <[email protected]>
* radv/ac: copy llvm machine feature flags from radeonsi.Dave Airlie2017-04-241-1/+1
| | | | | | | | This just updates this to use the same flags as radeonsi for consistency. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: remove now unused GLSL IR optimisationsTimothy Arceri2017-04-244-888/+0
| | | | | | | These are no longer used since the previous commit. Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: remove GLSL IR optimisation loopTimothy Arceri2017-04-241-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IVB is running into some spilling issues in piglit with the loop removed. However those tests are not really reflective of a real world use case, also fp64 is brand new to IVB so we leave the spilling issues to be resolved at a later time. Run time for shader-db on my machine goes from ~795 seconds to ~665 seconds. shader-db results BDW: total instructions in shared programs: 12969459 -> 12968891 (-0.00%) instructions in affected programs: 1463154 -> 1462586 (-0.04%) helped: 3622 HURT: 3326 total cycles in shared programs: 246453572 -> 246504318 (0.02%) cycles in affected programs: 208842622 -> 208893368 (0.02%) helped: 24029 HURT: 35407 total loops in shared programs: 2931 -> 2931 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total spills in shared programs: 14560 -> 14498 (-0.43%) spills in affected programs: 2270 -> 2208 (-2.73%) helped: 17 HURT: 2 total fills in shared programs: 19671 -> 19632 (-0.20%) fills in affected programs: 2060 -> 2021 (-1.89%) helped: 17 HURT: 2 LOST: 17 GAINED: 40 Most of the hurt shaders are 1-2 instructions, with what looks like a max of 7. I've looked at the worst cycles regressions and as far as I can tell its just a scheduling difference. Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: use ARB_enhahnced_layouts for packing where possibleTimothy Arceri2017-04-241-0/+70
| | | | | | | | | | | | | | | | | | | | | If packing doesn't cross locations we can easily make use of ARB_enhanced_layouts to do packing rather than using the GLSL IR lowering pass lower_packed_varyings(). Shader-db Broadwell results: total instructions in shared programs: 12977822 -> 12977819 (-0.00%) instructions in affected programs: 1871 -> 1868 (-0.16%) helped: 4 HURT: 3 total cycles in shared programs: 246567288 -> 246567668 (0.00%) cycles in affected programs: 1370386 -> 1370766 (0.03%) helped: 592 HURT: 733 Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: disable varying packing for varying used by interpolateAt*Timothy Arceri2017-04-243-7/+19
| | | | | | | | | | | | | | | | | Currently the NIR backends depend on GLSL IR copy propagation to fix up the interpolateAt* function params after varying packing changes the shader input to a global. It's possible copy propagation might not always do what we need it too, and we also shouldn't depend on optimisations to do this type of thing for us. I'm not sure if the same is true for TGSI, but the following commit should re-enable packing for most cases in a safer way, so we just disable it everywhere. No change in shader-db for i965 (BDW) Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_to_nir: skip ir_var_shader_shared variablesTimothy Arceri2017-04-241-0/+7
| | | | | | | | | | | | | | These should be lowered away in GLSL IR but if we don't get dead code to clean them up it causes issues in glsl_to_nir. We wan't to drop as many GLSL IR opts in future as we can so this makes glsl_to_nir just ignore the vars if it sees them. In future we will want to just use the nir lowering pass that Vulkan currently uses. Acked-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/i965: add before ffma algebraic optsTimothy Arceri2017-04-243-0/+30
| | | | | | | | | | | | | | | | | | | | | | | This shuffles constants down in the reverse of what the previous patch does and applies some simpilifications that may be made possible from doing so. Shader-db results BDW: total instructions in shared programs: 12980814 -> 12977822 (-0.02%) instructions in affected programs: 281889 -> 278897 (-1.06%) helped: 1231 HURT: 128 total cycles in shared programs: 246562852 -> 246567288 (0.00%) cycles in affected programs: 11271524 -> 11275960 (0.04%) helped: 1630 HURT: 1378 V2: mark float opts as inexact Reviewed-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: shuffle constants to the topTimothy Arceri2017-04-242-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | V2: mark float opts as inexact If one of the inputs to an mul/add is the result of another mul/add there is a chance that we can reuse the result of that mul/add in other calls if we do the multiplication in the right order. Also by attempting to move all constants to the top we increase the chance of constant folding. For example it is a fairly common pattern for shaders to do something similar to this: const float a = 0.5; in vec4 b; in float c; ... b.x = b.x * c; b.y = b.y * c; ... b.x = b.x * a + a; b.y = b.y * a + a; So by simply detecting that constant a is part of the multiplication in ffma and switching it with previous fmul that updates b we end up with: ... c = a * c; ... b.x = b.x * c + a; b.y = b.y * c + a; Shader-db results BDW: total instructions in shared programs: 13011050 -> 12967888 (-0.33%) instructions in affected programs: 4118366 -> 4075204 (-1.05%) helped: 17739 HURT: 1343 total cycles in shared programs: 246717952 -> 246410716 (-0.12%) cycles in affected programs: 166870802 -> 166563566 (-0.18%) helped: 18493 HURT: 7965 total spills in shared programs: 14937 -> 14560 (-2.52%) spills in affected programs: 9331 -> 8954 (-4.04%) helped: 284 HURT: 33 total fills in shared programs: 20211 -> 19671 (-2.67%) fills in affected programs: 12586 -> 12046 (-4.29%) helped: 286 HURT: 33 LOST: 39 GAINED: 33 Some of the hurt will go away when we shuffle things back down to the bottom in the following patch. It's also noteworthy that almost all of the spill changes are in Deus Ex both hurt and helped. Reviewed-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: add flt comparision simplificationTimothy Arceri2017-04-242-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | Didn't turn out as useful as I'd hoped, but it will help alot more on i965 by reducing regressions when we drop brw_do_channel_expressions() and brw_do_vector_splitting(). I'm not sure how much sense 'is_not_used_by_conditional' makes on platforms other than i965 but since this is a new opt it at least won't do any harm. shader-db BDW: total instructions in shared programs: 13029581 -> 13029415 (-0.00%) instructions in affected programs: 15268 -> 15102 (-1.09%) helped: 86 HURT: 0 total cycles in shared programs: 247038346 -> 247036198 (-0.00%) cycles in affected programs: 692634 -> 690486 (-0.31%) helped: 183 HURT: 27 Reviewed-by: Elie Tournier <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Enable lowering fdiv in nir.Bas Nieuwenhuizen2017-04-231-0/+1
| | | | | | | Results in faster code than the lowering by LLVM. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* freedreno/a5xx: hack for r8g8b8a8_snormRob Clark2017-04-231-1/+1
| | | | | | | | | Blob won't render to this format, and sampling from it it uses the same fmt value for r8g8b8_snorm and r8g8b8a8_snorm. But this is what is what blocks us from jumping from gl30/gles20 to gl31/gles30. So a hack it is! Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: rgtc formatsRob Clark2017-04-232-8/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* mesa: replace _mesa_index_buffer::type with index_sizeMarek Olšák2017-04-2220-94/+94
| | | | | | | This avoids repeated translations of the enum. Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Use the correct pipeline for dispatches.Bas Nieuwenhuizen2017-04-221-3/+3
| | | | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Fixes: ec15e0d30 "radv: optimise compute shader grid size emission." Tested-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* etnaviv: Supertiled texture support on gc3000Wladimir J. van der Laan2017-04-222-8/+11
| | | | | | | | | | | | | | | | | Support supertiled textures on hardware that has the appropriate feature flag SUPERTILED_TEXTURE. Most of the scaffolding was already in place in etna_layout_multiple: case ETNA_LAYOUT_SUPER_TILED: *paddingX = 64; *paddingY = 64; *halign = TEXTURE_HALIGN_SUPER_TILED; So this is just a matter of allowing it. Signed-off-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: etnaviv_fence: Simplify the return code logicFabio Estevam2017-04-221-4/+2
| | | | | | | The return code can be simplified by using the logical not operator. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* freedreno/a5xx: occlusion queryRob Clark2017-04-224-3/+140
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: drop ring arg from _set_stage()Rob Clark2017-04-227-17/+13
| | | | | | | | It is always the draw ring. Except for a5xx queries like time-elapsed, where we will eventually want to emit cmds into both binning and draw rings. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-04-226-12/+25
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add support for hw accumulating queriesRob Clark2017-04-228-33/+384
| | | | | | | | | | | | | Some queries on a4xx and all queries on a5xx can do result accumulation on CP so we don't need to track per-tile samples. We do still need to handle pausing/resuming while switching batches (in case the query is active over multiple draws which are executed out of order). So introduce new accumulated-query helpers for these sorts of queries, since it doesn't really fit in cleanly with the original query infra- structure. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a bit of query refactorRob Clark2017-04-224-40/+40
| | | | | | | | Move a bit more of the logic shared by all query types (active tracking, etc) into common code. This avoids introducing a 3rd copy of that logic for a5xx. Signed-off-by: Rob Clark <[email protected]>
* freedreno: make hw-query a helperRob Clark2017-04-2213-16/+57
| | | | | | | | | For a5xx (and actually some queries on a4xx) we can accumulate results in the cmdstream, so we don't need this elaborate mechanism of tracking per-tile query results. So make it into vfuncs so generation specific backend can use it when it makes sense. Signed-off-by: Rob Clark <[email protected]>
* i965/vec4: Avoid reswizzling MACH instructions in opt_register_coalesce().Kenneth Graunke2017-04-221-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | opt_register_coalesce() was optimizing sequences such as: mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D mach(8) vgrf5.xy:D, attr18.xyyy:D, attr19.xyyy:D mov(8) m4.zw:F, vgrf5.xxxy:F into: mul(8) acc0:D, attr18.xyyy:D, attr19.xyyy:D mach(8) m4.zw:D, attr18.xxxy:D, attr19.xxxy:D This doesn't work - if we're going to reswizzle MACH, we'd need to reswizzle the MUL as well. Here, the MUL fills the accumulator's .zw components with attr18.yy * attr19.yy. But the MACH instruction expects .z to contain attr18.x * attr19.x. Bogus results ensue. No change in shader-db on Haswell. Prevents regressions in Timothy's patches to use enhanced layouts for varying packing (which rearrange code just enough to trigger this pre-existing bug, but were fine themselves). Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: validate sampler type across the whole programTimothy Arceri2017-04-223-5/+28
| | | | | | | | | | | Currently we were only making sure types were the same within a single stage. This looks to have regressed with 953a0af8e3f73. Fixes: 953a0af8e3f73 ("mesa: validate sampler uniforms during gluniform calls") Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> https://bugs.freedesktop.org/show_bug.cgi?id=97524
* mesa: don't lock hashtables that are not shared across contextsTimothy Arceri2017-04-225-15/+16
| | | | | | | | | | | | | | | | | | | From Chapter 5 'Shared Objects and Multiple Contexts' of the OpenGL 4.5 spec: "Objects which contain references to other objects include framebuffer, program pipeline, query, transform feedback, and vertex array objects. Such objects are called container objects and are not shared" For we leave locking in place for framebuffer objects because the EXT fbo extension allowed sharing. We could maybe just replace the hash with an ordinary hash table but for now this should remove most of the unnecessary locking. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: Remove deleteFlag pattern from container objects.Matt Turner2017-04-222-6/+2
| | | | | | | | This pattern was only useful when we used mutex locks, which the previous commit removed. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: Remove unnecessary locking from container objects.Matt Turner2017-04-224-19/+0
| | | | | | | | | | | | | | | | | | | From Chapter 5 'Shared Objects and Multiple Contexts' of the OpenGL 4.5 spec: "Objects which contain references to other objects include framebuffer, program pipeline, query, transform feedback, and vertex array objects. Such objects are called container objects and are not shared" For we leave locking in place for framebuffer objects because the EXT fbo extension allowed sharing. V2: (Timothy Arceri) - rebased and dropped changes to framebuffer objects Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa: remove fallback RefCount == 0 patternTimothy Arceri2017-04-226-59/+25
| | | | | | | | We should never get here if this is 0 unless there is a bug. Replace the check with an assert. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* egl: add gitignoreElie TOURNIER2017-04-221-0/+2
| | | | | | | | | Since commit ce562f9e3fa, two new files are generated. We don't want to track them. Signed-off-by: Elie Tournier <[email protected]> Reviewed-by: Plamena Manolova <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl: make use of glsl_type::is_float()Samuel Pitoiset2017-04-2110-56/+48
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: make use of glsl_type::is_double()Samuel Pitoiset2017-04-2112-45/+45
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: make use of glsl_type::is_integer_64()Samuel Pitoiset2017-04-211-9/+2
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: simplify glsl_type::is_integer_32_64()Samuel Pitoiset2017-04-211-2/+1
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: add glsl_type::is_integer_64()Samuel Pitoiset2017-04-211-0/+8
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: make use of glsl_type::is_boolean()Samuel Pitoiset2017-04-214-19/+18
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: make use of glsl_type::is_record()Samuel Pitoiset2017-04-215-8/+6
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: make use of glsl_type::is_interface()Samuel Pitoiset2017-04-212-2/+2
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* glsl: make use of glsl_type::is_array()Samuel Pitoiset2017-04-215-5/+5
| | | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
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