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* anv: Move relocation handling from EndCommandBuffer to QueueSubmitJason Ekstrand2016-11-094-72/+76
* anv/batch: Move last_ss_pool_bo_offset to the command bufferJason Ekstrand2016-11-092-15/+24
* anv: Add an anv_execbuf helper structJason Ekstrand2016-11-092-48/+62
* anv/batch_chain: Improve write_relocJason Ekstrand2016-11-091-5/+22
* anv: Initialize anv_bo::offset to -1Jason Ekstrand2016-11-091-1/+1
* anv/allocator: Simplify anv_scratch_poolJason Ekstrand2016-11-092-61/+55
* anv: Add a new bo_pool_init helperJason Ekstrand2016-11-094-20/+21
* anv: Don't presume to know what address is in a surface relocationJason Ekstrand2016-11-092-53/+15
* anv: Add a cmd_buffer_execbuf helperJason Ekstrand2016-11-093-2/+11
* anv/device: Add an execbuf wrapperJason Ekstrand2016-11-092-20/+35
* anv: Make anv_finishme only warn once per call-siteJason Ekstrand2016-11-091-2/+7
* i965/compute: Allow ARB_compute_shader in compat profileJordan Justen2016-11-091-1/+1
* Revert "draw: use vectorized calculations for fetch"Roland Scheidegger2016-11-092-282/+159
* swr: disable logic op when the rt format is float or srgbIlia Mirkin2016-11-081-0/+6
* swr: fix AND_INVERTED logic op conversionIlia Mirkin2016-11-081-1/+1
* swr: add support for EXT_depth_bounds_testIlia Mirkin2016-11-082-1/+7
* swr: [rasterizer core] set depth hottile when depth bounds test enabledIlia Mirkin2016-11-081-1/+3
* i965: Fix GPU hang related to multiple render targets and alpha testingAnuj Phogat2016-11-081-0/+6
* swr: allow alphatest without blend or logicopTim Rowley2016-11-081-1/+2
* radv: emit correct last export when Z/stencil export is enabledDave Airlie2016-11-091-3/+5
* tgsi/scan: turn a huge if-else-if.. chain into a switch statementMarek Olšák2016-11-081-14/+30
* tgsi/scan: fix images_buffers regressionMarek Olšák2016-11-081-3/+2
* anv: Document cmd_buffer_alloc_binding_tableJason Ekstrand2016-11-081-0/+71
* intel/blorp: Emit all the binding tablesJason Ekstrand2016-11-081-0/+5
* i965/gen9: Allow sampling with hiz when supportedJordan Justen2016-11-081-1/+28
* i965/gen9: Add HiZ auxiliary buffer supportBen Widawsky2016-11-081-6/+14
* i965: Add function to indicate when sampling with hiz is supportedJordan Justen2016-11-083-1/+25
* i965/miptree: Create a hiz mcs typeBen Widawsky2016-11-085-41/+49
* i965: Drop the aux mt when not usedBen Widawsky2016-11-084-16/+46
* i965/miptree: Directly gtt map the mcs bufferBen Widawsky2016-11-081-2/+9
* i965: Wrap MCS miptree in intel_miptree_aux_bufferJordan Justen2016-11-084-59/+86
* gallivm: fix [IU]MUL_HI regressionNicolai Hähnle2016-11-083-28/+90
* draw: use vectorized calculations for fetchRoland Scheidegger2016-11-082-159/+282
* gallivm: introduce 32x32->64bit lp_build_mul_32_lohi functionRoland Scheidegger2016-11-083-38/+172
* i965: Add space before parenAnuj Phogat2016-11-071-1/+1
* i965: Remove unnecessary white spaceAnuj Phogat2016-11-071-1/+1
* i965: Fix alpha-to-coverage and alpha test enabled checksAnuj Phogat2016-11-074-12/+16
* mesa: Add helper function _mesa_is_alpha_to_coverage_enabled()Anuj Phogat2016-11-072-0/+16
* mesa: Add helper function _mesa_is_alpha_test_enabled()Anuj Phogat2016-11-072-0/+14
* mesa: Use separate line for function return typeAnuj Phogat2016-11-071-1/+2
* nvc0: simplify draw parameters upload for vertex shadersSamuel Pitoiset2016-11-071-8/+6
* gallium/hud: protect against and initialization raceSteven Toth2016-11-074-8/+41
* gallium/hud: close a previously opened handleSteven Toth2016-11-073-1/+6
* gallium/hud: fix a problem where objects are free'd while in use.Steven Toth2016-11-074-55/+0
* mesa: drop current draw/read buffer when ctx is releasedRob Clark2016-11-071-0/+4
* clover: Add CL_PROGRAM_BINARY_TYPE support (CL1.2).Serge Martin2016-11-0610-11/+35
* clover: add missing clGetDeviceInfo CL1.2 queriesSerge Martin2016-11-063-0/+35
* nvc0: get rid of NVE4_COMPUTE_MP_PM_{A,B}_SIGSEL_XXXSamuel Pitoiset2016-11-051-56/+56
* gm107/ir: emit RED instead of ATOM when no dstSamuel Pitoiset2016-11-051-1/+28
* st/mesa: initialize members of glsl_to_tgsi_instruction in emit_asm()Brian Paul2016-11-051-0/+4
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