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* nv50/ir: improve maintainability of Target*::initOpInfo()Rhys Perry2018-06-292-23/+28
* nv50/ir: fix image stores with indirect handlesRhys Perry2018-06-291-4/+5
* egl: fix build race in automakeRoss Burton2018-06-291-0/+1
* radeonsi: implement vertex color clamping for tess and GSMarek Olšák2018-06-284-33/+87
* radeonsi: move VS_STATE_SGPR before draw SGPRsMarek Olšák2018-06-282-10/+13
* radeonsi: don't use malloc in si_generate_gs_copy_shaderMarek Olšák2018-06-281-10/+2
* radeonsi: disable DCC statistics gathering on everything but StoneyMarek Olšák2018-06-281-3/+2
* radeonsi: don't enable DCC statistics gathering for small surfacesMarek Olšák2018-06-281-14/+16
* radeonsi: simplify logic around vi_separate_dcc_try_enableMarek Olšák2018-06-282-14/+15
* radeonsi: fix memory exhaustion issue with DCC statistics gathering with DRI2Marek Olšák2018-06-281-3/+27
* radeonsi: remove references to EvergreenMarek Olšák2018-06-284-4/+2
* radeonsi: enable shader caching for compute shadersMarek Olšák2018-06-283-15/+50
* radeonsi: store compute local_size into tgsi_shader_infoMarek Olšák2018-06-284-6/+10
* radeonsi: unify duplicated code for initial shader compilationMarek Olšák2018-06-283-43/+39
* ac: set +auto-waitcnt-before-barrier when neededMarek Olšák2018-06-281-2/+4
* radeonsi/gfx9: insert the barrier between merged shaders inside the if blockMarek Olšák2018-06-281-5/+13
* gallium: plumb invariant output attrib thru TGSIJoe M. Kniss2018-06-296-15/+45
* intel/fs: Build 32-wide FS shaders.Francisco Jerez2018-06-281-11/+43
* intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaroundJason Ekstrand2018-06-283-2/+49
* intel/fs: Add fields to wm_prog_data for SIMD32 dispatchJason Ekstrand2018-06-286-1/+15
* intel/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32.Francisco Jerez2018-06-281-5/+9
* intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.Francisco Jerez2018-06-281-3/+3
* intel/fs: Fix Gen6+ interpolation setup for SIMD32Francisco Jerez2018-06-281-56/+60
* intel/fs: Get rid of MOV_DISPATCH_TO_FLAGSJason Ekstrand2018-06-285-35/+8
* intel/fs: Emit MOV_DISPATCH_TO_FLAGS once for the centroid workaroundJason Ekstrand2018-06-282-50/+16
* intel/fs: Generalize the unlit centroid workaroundFrancisco Jerez2018-06-281-14/+8
* intel/fs: Fix sample id setup for SIMD32.Francisco Jerez2018-06-281-9/+25
* intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32Francisco Jerez2018-06-281-1/+7
* intel/fs: Implement 32-wide FS payload setup on Gen6+Francisco Jerez2018-06-281-67/+57
* intel/fs: Extend thread payload layout to SIMD32Francisco Jerez2018-06-283-22/+45
* intel/fs: Wrap FS payload register look-up in a helper function.Francisco Jerez2018-06-283-12/+23
* intel/fs: Use fs_regs instead of brw_regs in the unlit centroid workaroundFrancisco Jerez2018-06-281-12/+12
* intel/fs: Simplify fs_visitor::emit_samplepos_setupFrancisco Jerez2018-06-281-21/+7
* i965: Add plumbing for shader time in 32-wide FS dispatch mode.Francisco Jerez2018-06-287-5/+15
* intel/fs: Disable opt_sampler_eot() in 32-wide dispatch.Francisco Jerez2018-06-282-1/+6
* intel/fs: Emit LINE+MAC for LINTERP with unaligned coordinatesJason Ekstrand2018-06-282-10/+56
* intel/fs: Mark LINTERP opcode as writing accumulator on platforms without PLNJason Ekstrand2018-06-281-1/+2
* intel/fs: Rework INTERPOLATE_AT_PER_SLOT_OFFSETFrancisco Jerez2018-06-283-19/+9
* intel/fs: Add the group to the flag subreg number on SNB and olderJason Ekstrand2018-06-281-1/+7
* intel/fs: Fix FB read header setup for SIMD32.Francisco Jerez2018-06-281-4/+13
* intel/fs: Fix logical FB write lowering for SIMD32Francisco Jerez2018-06-281-5/+20
* intel/fs: Fix FB write message control codegen for SIMD32.Francisco Jerez2018-06-281-18/+34
* intel/fs: Don't enable dual source blend if no outputs are writtenFrancisco Jerez2018-06-281-1/+2
* intel/fs: Fix codegen of FS_OPCODE_SET_SAMPLE_ID for SIMD32.Francisco Jerez2018-06-281-11/+13
* intel/eu: Fix pixel interpolator queries for SIMD32.Francisco Jerez2018-06-281-1/+2
* intel/fs: Disable SIMD32 dispatch for fragment shaders with discard.Francisco Jerez2018-06-281-0/+2
* intel/fs: Disable SIMD32 dispatch on Gen4-6 with control flowFrancisco Jerez2018-06-281-0/+8
* intel/fs: Split instructions low to high in lower_simd_widthJason Ekstrand2018-06-281-2/+35
* intel/fs: Rework KSP data to be SIMD width-basedJason Ekstrand2018-06-283-47/+43
* intel/compiler: Add and use helpers for working with KSP indicesJason Ekstrand2018-06-285-55/+183
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