summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* nv50: move onto shared fence codeBen Skeggs2011-03-0110-347/+45
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nouveau: move nv50/nvc0 fencing to common location, and modify slightlyBen Skeggs2011-03-015-4/+296
| | | | | | | Modified from original to remove chipset-specific code, and to be decoupled from the mm present in said drivers. Signed-off-by: Ben Skeggs <[email protected]>
* nv50-nvc0: set cur_ctx during init if none currently boundBen Skeggs2011-03-012-0/+4
| | | | Signed-off-by: Ben Skeggs <[email protected]>
* nv50: replace most of it with nvc0 driver ported to nv50Christoph Bumiller2011-02-2841-6621/+8825
| | | | We'll have to do some unification now to reduce code duplication.
* r300g: disable hyper-z on rs6xx+Marek Olšák2011-02-281-6/+0
| | | | It doesn't work.
* mesa: Add texcompress_rgtc.c to SConscript.Vinson Lee2011-02-271-0/+1
|
* mesa/st: add RGTC format support.Dave Airlie2011-02-282-0/+33
| | | | this just adds a format check + format conversion.
* swrast: add RGTC supportDave Airlie2011-02-282-0/+20
|
* mesa: Add RGTC texture store/fetch support.Dave Airlie2011-02-288-3/+1287
| | | | | | | | | This adds support for the RGTC unsigned and signed texture storage and fetch methods. the code is a port of the DXT5 alpha compression code. Signed-off-by: Dave Airlie <[email protected]>
* mesa: make_float_temp_image non-staticDave Airlie2011-02-282-23/+32
| | | | We need this to do signed stuff for RGTC.
* rgtc: llvmpipe/softpipe refuse RGTC until u_format has support.Dave Airlie2011-02-282-0/+10
| | | | | | So far I haven't implemented the u_format code for these. Signed-off-by: Dave Airlie <[email protected]>
* r300g: force swizzles for RGTCDave Airlie2011-02-281-0/+5
| | | | still can't get signed to work
* r600g: implement instanced drawing supportChristian König2011-02-286-103/+191
|
* st/mesa & v_bug_mgr: two small instanced drawing fixesChristian König2011-02-282-1/+6
|
* Revert "r600g: Don't negate result of ABS instruction"Dave Airlie2011-02-281-2/+0
| | | | | | This reverts commit b6d40213935da702570eca2c0861bd4b1d7f5254. This actually breaks gears here on my rv670.
* r600g: Process TRUNC with tgis_op2Fabian Bieler2011-02-281-2/+2
| | | | | | TRUNC is neither a scalar instruction nor exclusive to the Trans unit. Signed-off-by: Dave Airlie <[email protected]>
* r600g: Don't negate result of ABS instructionFabian Bieler2011-02-281-0/+2
| | | | Signed-off-by: Dave Airlie <[email protected]>
* i915g: implement cache flushingDaniel Vetter2011-02-276-8/+62
| | | | | | | | | | | With an extremely dumb strategy. But it's the same i915c employs. Also improve the hw_atom code slightly by statically specifying the required batch space. For extremely variably stuff (shaders, constants) it would probably be better to add a new parameter to the hw_atom->validate function. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: buffer validation for blitterDaniel Vetter2011-02-271-0/+11
| | | | Signed-off-by: Daniel Vetter <[email protected]>
* i915g: buffer validation for render stateDaniel Vetter2011-02-273-0/+87
| | | | | | | | Also contains the first few bits for hw state atoms. v2: Implement suggestion by Jakob Bornecrantz. Signed-off-by: Daniel Vetter <[email protected]>
* i915g/winsys: buffer validation supportDaniel Vetter2011-02-273-0/+42
| | | | | | | v2: Add the batch bo to the libdrm validation lost, for otherwise libdrm won't take previously used buffers into account. Signed-off-by: Daniel Vetter <[email protected]>
* i915g: add raw batchbuffer dumping in drm winsysDaniel Vetter2011-02-273-0/+11
| | | | | | | | | These files can be decoded with intel_dump_decode from the intel-gpu-tools available at: http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/ Signed-off-by: Daniel Vetter <[email protected]>
* i915g: cleanup static state calculation, part 2Daniel Vetter2011-02-273-48/+48
| | | | | | Now also for the DRAW_RECT command Signed-off-by: Daniel Vetter <[email protected]>
* i915g: cleanup static state calculation, part 1Daniel Vetter2011-02-273-89/+103
| | | | | | | Move it to i915_state_static.c This way i915_emit_state.c only emits state and doesn't (re)calculate it. Signed-off-by: Daniel Vetter <[email protected]>
* glsl/builtins: Fix return type for textureSize sampler2DArray variants.Kenneth Graunke2011-02-272-4/+4
| | | | A copy and paste error.
* intel: Use the current context rather than last bound context for a drawable.Eric Anholt2011-02-261-1/+2
| | | | | | | | If another thread bound a context to the drawable then unbound it, the driContextPriv would end up NULL. With the previous two fixes, this fixes glx-multithread-makecurrent-2, despite the issue not being about the multithreaded makecurrent.
* dri2: Don't call the dri2 flush hook for swapbuffers unless we have a context.Eric Anholt2011-02-261-2/+7
| | | | | | The driver only has one reasonable place to look for its context to flush anything, which is the current context. Don't bother it with having to check.
* glx: Don't do the implicit glFlush in SwapBuffers if it's the wrong drawable.Eric Anholt2011-02-261-2/+6
| | | | | The GLX Spec says you only implicitly glFlush if the drawable being swapped is the current context's drawable.
* mesa: Add new MESA_multithread_makecurrent extension.Eric Anholt2011-02-264-24/+37
| | | | | | | This extension allows a client to bind one context in multiple threads simultaneously. It is then up to the client to manage synchronization of access to the GL, just as normal multithreaded GL from multiple contexts requires synchronization management to shared objects.
* i915g: make dynamic state emission actually lazyDaniel Vetter2011-02-261-1/+1
| | | | | | Premature semicolon. Signed-off-by: Daniel Vetter <[email protected]>
* gallivm: Initialize stack valuesJakob Bornecrantz2011-02-261-8/+8
| | | | | valgrind gives me a warning with llvmpipe with profile builds but not debug builds, this seems to fix the issue at least.
* glsl/Makefile: Remove builtin_function.cpp if generation fails.Arkadiusz Miskiewicz2011-02-261-1/+1
| | | | | | Fixes bug #34346. Signed-off-by: Kenneth Graunke <[email protected]>
* i915g: Handle null constants properlyJakob Bornecrantz2011-02-261-3/+6
|
* i915g: fix null deref in draw_rect emissionDaniel Vetter2011-02-261-4/+8
| | | | Signed-off-by: Daniel Vetter <[email protected]>
* i915g: simplify math in constants emissionDaniel Vetter2011-02-261-1/+1
| | | | | | The old code even falls apart for nr == 0 (which is caught earlier, but)! Signed-off-by: Daniel Vetter <[email protected]>
* i915g: Use the same debug env vars in drm and sw winsysJakob Bornecrantz2011-02-261-1/+1
|
* i915g: Use unchecked writes in sw winsys batchbufferJakob Bornecrantz2011-02-261-3/+3
|
* Check for out of memory when creating fenceAlan Hourihane2011-02-261-0/+3
|
* util: Don't destroy shaders null shadersJakob Bornecrantz2011-02-261-2/+4
| | | | Fixes regression from a08e612fd8e7ca2ac2fef8961e56e5b094033717
* util: Don't create array texture shaders if the driver doesn't support itJakob Bornecrantz2011-02-261-4/+6
|
* i965/fs: Initial plumbing to support TXD.Kenneth Graunke2011-02-252-0/+14
| | | | | This adds the opcode and the code to convert ir_txd to OPCODE_TXD; it doesn't actually add support yet.
* i965/fs: Complete TXL support on gen5+.Kenneth Graunke2011-02-251-0/+7
| | | | | Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
* i965/fs: Complete TXL support on gen4.Kenneth Graunke2011-02-251-0/+10
| | | | | Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
* i965/fs: Use a properly named constant in TXB handling.Kenneth Graunke2011-02-251-1/+1
| | | | | | | The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're doing a non-bias texture lookup. It has the same value as the new constant BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no functional changes.
* i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke2011-02-251-0/+2
| | | | From volume 4, page 161 of the public i965 documentation.
* gallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issueJerome Glisse2011-02-251-14/+14
| | | | | | | | | | | | There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa due to ureg_src size, reshuffling the structure member to better better alignment work around the issue. http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893 7.9 + 7.10 candidate Signed-off-by: Jerome Glisse <[email protected]>
* gallium/st: place value check before value is useJerome Glisse2011-02-251-1/+1
| | | | | | 7.9 & 7.10 candidate Signed-off-by: Jerome Glisse <[email protected]>
* gallium/util: add 1d/2d mipmap generation supportDave Airlie2011-02-251-6/+37
| | | | | | | | so far only hw mipmap generation is testing on softpipe, passes test added to piglit. this requires another patch to mesa to let array textures mipmaps even start to happen.
* scons: Reduce all Cygwin platform names to 'cygwin'.Vinson Lee2011-02-241-1/+1
| | | | | | | | | | | platform.system in SCons on Cygwin includes the OS version number. Windows XP - CYGWIN_NT-5.1 Windows Vista - CYGWIN_NT-6.0 Windows 7 - CYGWIN_NT-6.1 Reduce all Cygwin platform variants to just 'cygwin' so anything downstream can simply use 'cygwin' instead of the different full platform names.
* r600g: explicity set sign bits for RGTCDave Airlie2011-02-251-2/+4
|
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 20:37:57 +0000