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* anv: Move clamp_int64() inside the IVB checkMatt Turner2017-08-211-1/+1
| | | | | | It's only used in the gen7_cmd_buffer_emit_scissor() function. Reviewed-by: Jordan Justen <[email protected]>
* glsl: Remove unused private fieldsMatt Turner2017-08-212-5/+2
| | | | Reviewed-by: Jordan Justen <[email protected]>
* mesa: Don't compare unsigned for < 0Matt Turner2017-08-211-1/+1
| | | | | | | | | | | | | The INTEL_performance_query spec says "Performance counter id 0 is reserved as an invalid counter." GLuint counterid_to_index(GLuint counterid) just returns counterid - 1, so with unsigned overflow rules, it will generate 0xFFFFFFFF given an input of 0. 0xFFFFFFFF will trigger the counterIndex >= queryNumCounters check, so the code worked as is. It just contained a useless comparison. Reviewed-by: Jordan Justen <[email protected]>
* egl: Fix inclusion of egl.h+mesa_glinterop.hMatt Turner2017-08-212-2/+2
| | | | | | | | Previously clang would warn about redefinition of typedef EGLDisplay. Avoid this by adding preprocessor guards to mesa_glinterop.h and including it after EGL.h is indirectly included. Reviewed-by: Jordan Justen <[email protected]>
* radeonsi: don't prefetch VBO descriptors if vertex elements == NULLMarek Olšák2017-08-212-1/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: don't set up and don't call the fetch shader if there are no VS inputsMarek Olšák2017-08-213-1/+7
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* i965: Optimize reading the destination typeMatt Turner2017-08-211-1/+3
| | | | | | | | | | | | | brw_hw_type_to_reg_type() needs to know only whether the file is BRW_IMMEDIATE_VALUE or not, which is not a valid file for the destination. gcc and clang will evaluate __builtin_strcmp() at compile time, so we can use it to pass a constant file for the destination. text data bss dec hex filename 7816214 346248 420496 8582958 82f72e i965_dri.so before 7816070 346248 420496 8582814 82f69e i965_dri.so after Reviewed-by: Scott D Phillips <[email protected]>
* i965: Mark brw_hw_type_to_reg_type() as a pure functionMatt Turner2017-08-211-1/+7
| | | | | | | | text data bss dec hex filename 7816886 346248 420496 8583630 82f9ce i965_dri.so before 7816214 346248 420496 8582958 82f72e i965_dri.so after Reviewed-by: Scott D Phillips <[email protected]>
* i965: Hide the register type hardware encodingsMatt Turner2017-08-212-31/+31
| | | | | | So we stop mixing them with the logical enum. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Stop using hardware register types directlyMatt Turner2017-08-214-158/+113
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.cMatt Turner2017-08-213-39/+45
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Move brw_reg_type_letters() as wellMatt Turner2017-08-216-33/+37
| | | | | | | And add "to_" to the name for consistency with the other functions in this file. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Switch to using the logical register typesMatt Turner2017-08-212-21/+19
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add functions to abstract access to register typesMatt Turner2017-08-212-51/+79
| | | | | | | | | | | | | | | | | | Previously the brw_inst{,_set}_{dst,src0,src1}_reg_type() functions provided access to the hardware encodings for the register types. We often mixed these with the logical BRW_REGISTER_TYPE_* enums (which themselves used to be the hardware format!) with bad results. With that functionality now available with the hw_ versions (see previous commit), we now add functions that take the logical BRW_REGISTER_TYPE_* enums and convert into the hardware format and vice versa. To do the conversion we also have to provide the file. Note the asymmetry between the two functions: the new getter reads the file from the instruction word, and to ensure that is always set the setter writes both the file and the type. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Rename brw_inst's functions that access the register typeMatt Turner2017-08-217-99/+99
| | | | | | Put hw_ in the name so that it's clear these are the hardware encodings. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Index brw_hw_reg_type_to_size()'s table by logical typeMatt Turner2017-08-211-39/+19
| | | | | | I'll be transitioning everything to use the logical types. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add a brw_hw_type_to_reg_type() functionMatt Turner2017-08-212-0/+29
| | | | | | Will be used in later commits. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Use a common table to translate logical to hardware typesMatt Turner2017-08-211-36/+29
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Extract functions dealing with register types to separate fileMatt Turner2017-08-215-140/+209
| | | | | | | | | | I'm going to encapsulate all of the logic dealing with register types in this file. Rename the parameters for the hardware encodings from type -> hw_type at the same time. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Reverse file/type arguments to register type functionsMatt Turner2017-08-214-13/+15
| | | | | | | I think of the initial arguments as "state" and the last as the actual subject. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Add support for disassembling 64-bit integer immediatesMatt Turner2017-08-212-0/+13
| | | | | | | After the last patch converted things into enums, I helpfully got a compiler warning about these missing from the switch statement. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Use separate enums for register vs immediate typesMatt Turner2017-08-216-129/+144
| | | | | | | The hardware encodings often mean different things depending on whether the source is an immediate. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Reorder brw_reg_type enum valuesMatt Turner2017-08-215-26/+21
| | | | | | | | | | | These vaguely corresponded to the hardware encodings, but that is purely historical at this point. Reorder them so we stop making things "almost work" when mixing enums. The ordering has been closen so that no enum value is the same as a compatible hardware encoding. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Validate destination restrictions with vector immediatesMatt Turner2017-08-213-12/+141
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Don't let raw-move check be tricked by immediate vector typesMatt Turner2017-08-211-3/+10
| | | | | | | UB and B type encodings are the same as UV and VF. Noticed when writing the following patch. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Only change type of 0.0f to VF if destination stride == 1Matt Turner2017-08-211-1/+2
| | | | | | | | | | The destination stride must be equivalent to a dword if VF is used. Also, since the only compaction table entires with "i:vf" have the destination as "r:f" specifically check that the destination is of type float. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Remove CONT/BREAK from instruction compaction testMatt Turner2017-08-211-4/+0
| | | | | | | These cannot be compacted. A similar mistake was fixed in commit 90eaf01616a8 Reviewed-by: Scott D Phillips <[email protected]>
* i965: Test instruction compaction on all supported GensMatt Turner2017-08-211-8/+42
| | | | | | | | Note that there's no point in testing on G45, since its compaction is the same as Gen5. Same logic applies to Gen7 variants and low-power parts. Reviewed-by: Scott D Phillips <[email protected]>
* i965: Silence signed/unsigned comparison warningMatt Turner2017-08-211-1/+1
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Move compaction "prepass" into brw_eu_compact.cMatt Turner2017-08-212-72/+82
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* i965: Mark src inst pointer const in compaction codeMatt Turner2017-08-212-12/+13
| | | | Reviewed-by: Scott D Phillips <[email protected]>
* vulkan: import 1.0.59 headers and xml.Dave Airlie2017-08-221-8/+45
| | | | Acked-by: Jason Ekstrand <[email protected]>
* Android: Fix LLVM duplicated symbols linking for N and MRob Herring2017-08-213-5/+3
| | | | | | | | | | | | | | | | | | | | | Both statically linking libLLVMCore and dynamically linking libLLVM causes duplicated symbols in gallium_dri.so and it fails to dlopen. We don't really need to link libLLVMCore, but just need generated headers to be built first. Dynamically linking to libLLVM instead is enough to do that. Thanks to Qiang Yu for finding the root cause. With this change, we can align all versions and just have libLLVM as a shared lib dependency. This also requires changes in the M and N versions of LLVM to export the include paths for libLLVM. AOSP master is okay. Fixes: 26aee6f4d5a ("Android: rework LLVM build support") Reported-by: Mauro Rossi <[email protected]> Cc: 17.2 <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Qiang Yu <[email protected]> Signed-off-by: Rob Herring <[email protected]>
* st/va: add MJPEG for configLeo Liu2017-08-212-1/+5
| | | | | | | To enable MJPEG HW decode Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: reallocate surface with YUYV streamLeo Liu2017-08-211-0/+17
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: detect MJPEG format from bitstreamLeo Liu2017-08-213-0/+10
| | | | | | | | | To find if the format is supported YUYV by sampling factor which is embedded from bitstream. So we could use this info for buffer reallocation on the correct format. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: add YUYV format support for target bufferLeo Liu2017-08-212-3/+5
| | | | | | | Make chroma plane optional for YUYV support Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: reallocate surface when interlacedLeo Liu2017-08-211-0/+22
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/video: MJPEG not support stacked video buffersLeo Liu2017-08-211-1/+5
| | | | | | | So we have to detect it for reallocation of de-interlaced buffers Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: make surface allocate functions more usefullyLeo Liu2017-08-212-4/+5
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: reconstruct MJPEG bitstreamLeo Liu2017-08-211-0/+136
| | | | | | | | | The current tier 1 mjpeg firmware only supports at the bitstream level, the later tier 2 support will be at the buffers level with newer hardware. Signed-off-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]>
* st/va: add slice parameter handling for MJPEGLeo Liu2017-08-211-1/+23
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add huffman table handling for MJPEGLeo Liu2017-08-211-1/+18
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add iq matrix handling for MJPEGLeo Liu2017-08-211-1/+6
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add picture parameter handling for MJPEGLeo Liu2017-08-211-1/+20
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add handles for MJPEG BuffersLeo Liu2017-08-214-0/+72
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: create decoder for MJPEG formatLeo Liu2017-08-211-3/+6
| | | | | | | Mjpeg doesn't need reference Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/va: add MJPEG picture to contextLeo Liu2017-08-211-0/+1
| | | | | Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/video: add MJPEG supportLeo Liu2017-08-211-0/+8
| | | | | | | v2: add ASIC and Kernel version check Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/uvd: add MJPEG supportLeo Liu2017-08-211-9/+22
| | | | | | | | | There is no need of dpb buffer for mjpeg codec v2: check dpb_size instead of format Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
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