| Commit message (Collapse) | Author | Age | Files | Lines |
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Reviewed-by: Samuel Pitoiset <[email protected]>
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Fixes arb_vertex_buffer_object-combined-vertex-index
Cc: [email protected]
Signed-off-by: Dave Airlie <[email protected]>
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Fixes a drawable leak.
Fixes: bbc29393d3be ("st/mesa: create framebuffer iface hash table per
st manager")
Bugzilla: https://bugs.freedesktop.org/101930
Tested-by: Nick Sarnie <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
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This ports 72e46c988 to radv.
radeonsi: apply a TC L1 write corruption workaround for SI
Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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We were adding pad to size after creating the object, so we could
submit a CS bigger than the bo created for it.
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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This ports: da7453666ae
radeonsi: don't apply the Z export bug workaround to Hainan
to radv.
Just noticed in passing.
Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
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We already have this little optimization for color clears. Now that
we're actually tracking whether or not a slice has any fast-clear
blocks, it's easy enough to add for depth clears too.
Improves performance of GFXBench 4 TRex at 1920x1080 by:
- Skylake GT4: 0.905932% +/- 0.0620197% (n = 30)
- Apollolake: 0.382434% +/- 0.1134730% (n = 25)
v2: (by Ken) Rebase and drop intel_mipmap_tree.c changes, as they're
no longer necessary (other patches already landed to do that part)
Reviewed-by: Kenneth Graunke <[email protected]>
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When changing the clear value, we need to resolve any fast cleared data.
Previously, we were performing resolves on every slice with HiZ enabled.
We only need to resolve slices that a) have fast clear data, and b)
aren't about to be cleared to the new color. In the latter case, we
were actually doing a resolve, and then a fast clear - when we could
skip both, causing the existing fast cleared area to be updated to the
new clear value for no additional work.
This patch stops using intel_miptree_prepare_access in favor of a more
optimal open coded loop that knows about our clear operation.
v2: (by Ken) Rebase on islification, write a real commit message.
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
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I want to use it in brw_clear.c.
Reviewed-by: Lionel Landwerlin <[email protected]>
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v2: don't do it for compressed textures (bpp = 0)
Cc: 17.2 <[email protected]>
Reviewed-by: Alex Deucher <[email protected]> (v1)
Reviewed-by: Nicolai Hähnle <[email protected]> (v1)
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Cc: 17.2 <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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This fixes a bug uncovered by:
2412c4c81ea0488df865817a0de91ec46e359b72
util: Make CLAMP turn NaN into MIN.
Cc: 17.2 <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
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Noticed by James Legg @ Feral.
Cc: 17.2 <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
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From 25-26 min fps to 31, used the game in conjuction with a mod (full
invasion 2) beaumaris castle map and 200 bots.
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We'll fail to flag an error if the context flags appear after the
no-error attribute in the context attribute list.
Delay the check to after attribute parsing to fix this.
Fixes: 4909519a665 ("egl: Add EGL_KHR_create_context_no_error support")
Cc: [email protected]
[Emil Velikov: add fixes/stable tags, commit message polish]
Reviewed-by: Emil Velikov <[email protected]>
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We have a few UUIDs, so lets be more specific.
Signed-off-by: Andres Rodriguez <[email protected]>
Reviewed-by: Timothy Arceri <[email protected]>
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The number of supported waves per thread group has been reduced to 16
with gfx9. Trying to use 32 waves causes hangs, and barriers might
not work correctly with > 16 waves.
Cc: [email protected]
Reviewed-by: Marek Olšák <[email protected]>
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The firmware version numbers for SI were wrong. The new numbers are probably
too conservative (we don't have a definitive answer by the firmware team),
but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on
Tahiti (by Gustaw) and on Verde (by myself).
While this is technically adding a feature, it's a feature we thought we had
for a long time. The change is small enough and we're early enough in the 17.2
release cycle that it should still go in.
Reported-by: Gustaw Smolarczyk <[email protected]>
Cc: 17.2 <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs.
However, the maximum allowed value of "Vertex URB Entry Read Length"
in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements.
Because we also need to reserve a vertex buffer to upload
VertexIndex/InstanceIndex and another to upload DrawID when needed,
we can only expose 28.
Cc: "17.2" <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
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Cc: "17.2" <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
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Here the AUX_USAGE_* mode indicates that we have HiZ, so we will have
a HiZ buffer. But Coverity doesn't know that, so it thinks it might
be NULL because we checked hiz_buf != NULL earlier.
Reviewed-by: Jason Ekstrand <[email protected]>
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Caught by Coverity (CID 1415680).
Cc: "17.2" <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
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Increase the value, not the pointer to the stack variable.
Caught by Coverity (CID 1415574). Not shipped in a real release.
Cc: "17.2" <[email protected]>
Reviewed-by: Topi Pohjolainen <[email protected]>
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No changes, just re-indent.
Signed-off-by: Andres Rodriguez <[email protected]>
Reviewed-by: Timothy Arceri <[email protected]>
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This allows us to drop the duplicate gl_uniform_block_packing enum.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Reviewed-by: Grazvydas Ignotas <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Grazvydas Ignotas <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Grazvydas Ignotas <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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NewBufferObj() is called when the shared state is allocated so we
wouldn't get this far if it was NULL.
Reviewed-by: Samuel Pitoiset <[email protected]>
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This avoids useless error checking.
Reviewed-by: Samuel Pitoiset <[email protected]>
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Reviewed-by: Samuel Pitoiset <[email protected]>
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It should have been created by this point.
Reviewed-by: Samuel Pitoiset <[email protected]>
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This keeps the flags out of v3d_decode.c's output. In the generated code,
only the unpack functions see any change (where they now get the
restricted start value), and vc4 doesn't use the unpack functions yet.
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I was writing the XML such that the address field overlapped various flags
in the alignment bits, which caused pain when trying to unpack for decode.
Instead, keep the XML matching the docs (address fields don't overlap),
and just infer the appropriate shift value during decode.
During pack, the address is just applied to the appropriate bits
already, ignoring the sub-byte start/end fields.
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We simply pick r4 if available (anything else would force a MOV), then
round-robin through accumulators (avoids physical regfile RAW delay
slots), then round-robin through the physical regfile.
The effect on instruction count is pretty impressive:
total instructions in shared programs: 76563 -> 74526 (-2.66%)
instructions in affected programs: 66463 -> 64426 (-3.06%)
and we could probably do better with a little heuristic of "if we're going
to choose a physical reg, and other operands of instructions using this as
a src have the same physical regfile, then use the other regfile".
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VC4 has had a tension, similar to pre-Sandybridge Intel, where we want to
use low-numbered registers (more parallelism on Intel, fewer delay slots
on vc4), but in order to give instruction scheduling the most freedom to
avoid delays we want to round-robin between registers of the same cost.
Our two heuristics so far have chosen one end or the other of that
tradeoff.
The callback, instead, hands the driver the set of registers that are
available, and the driver gets to make its own choice. This will be used
in vc4 to round-robin between registers of the same cost, and might be
used in the future for improving bank selection.
Reviewed-by: Nicolai Hähnle <[email protected]>
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All the paths looping over adjacency had guards against considering
themselves (the non-obvious one was ra_any_neighbors_conflict(), which has
in_stack set).
Reviewed-by: Nicolai Hähnle <[email protected]>
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I was going to indent this code another level, and decided it would be
easier to read as a helper.
Reviewed-by: Nicolai Hähnle <[email protected]>
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Without this, a BlitFramebuffer would mark the whole framebuffer as being
changed (so we emit loads/stores of all of it) rather than just the
modified subset.
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I don't know how I managed to leave this here for so long. Found when
working on a 1:1 overlapping blit extension for X11.
Cc: [email protected]
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This gets us automatic CL decoding to a floating-point value, and drops a
magic number from the emit code. 250x250 shader runner tests now say they
have a center of 125.0 instead of 2000.
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The VC4_DEBUG_CL output goes from:
0x00000010 0x00000010: 0x06 VC4_PACKET_START_TILE_BINNING
0x00000011 0x00000011: 0x38 VC4_PACKET_PRIMITIVE_LIST_FORMAT
0x00000012 0x00000012: 0x12
0x00000013 0x00000013: 0x66 VC4_PACKET_CLIP_WINDOW
0x00000014 0x00000014: 0x00
0x00000015 0x00000015: 0x00
0x00000016 0x00000016: 0x00
0x00000017 0x00000017: 0x00
0x00000018 0x00000018: 0xfa
0x00000019 0x00000019: 0x00
0x0000001a 0x0000001a: 0xfa
0x0000001b 0x0000001b: 0x00
to:
0x00000010 0x00000010: 0x06 Start Tile Binning
0x00000011 0x00000011: 0x38 Primitive List Format
Data Type: 1 (16-bit index)
Primitive Type: 2 (Triangles List)
0x00000013 0x00000013: 0x66 Clip Window
Clip Window Height in pixels: 250
Clip Window Width in pixels: 250
Clip Window Bottom Pixel Coordinate: 0
Clip Window Left Pixel Coordinate: 0
v2: Squash in robher's fixes for Android
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This is copied from Intel's XML decoder, modified to handle V3D's
byte-oriented packets.
v2: Squash in robher's fixes for Android
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This is the same 8-space style used in the vc4 and vc5 gallium drivers.
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Reviewed-by: Lionel Landwerlin <[email protected]>
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Reviewed-by: Lionel Landwerlin <[email protected]>
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The device doesn't directly support this feature so we implement it with
additional shader code which sets the color output(s) w component to
1.0 (or max_int or max_uint).
Fixes 16 Piglit ext_framebuffer_multisample/*alpha-to-one* tests.
v2: only support unorm/float buffers, not int/uint, per Roland.
Reviewed-by: Roland Scheidegger <[email protected]>
Reviewed-by: Charmaine Lee <[email protected]>
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When we forcibly write white to FS outputs (for XOR mode emulation)
we were using a temp register. But that's not really necessary.
This also fixes the case of writing white to multiple color buffers.
Subsequent changes will build on this.
Reviewed-by: Charmaine Lee <[email protected]>
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Reviewed-by: Roland Scheidegger <[email protected]>
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