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* radeon/vcn: fix mpeg4 msg buffer settingsBoyuan Zhang2018-05-021-9/+9
| | | | | | | | | Previous bit-fields assignments are incorrect and will result certain mpeg4 decode failed due to wrong flag values. This patch fixes these assignments. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> (cherry picked from commit deba56accf4e1f8fc025f34f6cbc069285f76838)
* i965/tex_image: Avoid the ASTC LDR workaround on gen9lpNanley Chery2018-05-021-1/+1
| | | | | | | | | | | | Both the internal documentation and the results of testing this in the CI suggest that this is unnecessary. Add the fixes tag because this reduces an internal benchmark's startup time by about 17 seconds (reported by Eero). Fixes: 710b1d2e665 "i965/tex_image: Flush certain subnormal ASTC channel values" Tested-by: Eero Tamminen <[email protected]> Acked-by: Kenneth Graunke <[email protected]> (cherry picked from commit 3e56e4642fb5875b3f5c4eb34798ba9f3d827705)
* radv: compute the number of subpass attachments correctlySamuel Pitoiset2018-05-021-2/+2
| | | | | | | | | | Only count color attachments twice if resolves are used, also account for the depth stencil attachment if present. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> (cherry picked from commit d8db5986cee83078e46895d695d698db87507019)
* radv/winsys: fix leaking resources from bo's imported by fdAndres Rodriguez2018-05-021-0/+1
| | | | | | | | | | | | | A bo's ref_count was not being initialized when imported from an fd. Therefore, we would fail to free the resource during VkFreeMemory(). This patch fixes applications like hifi VR in threaded mode, which perform frequent imports/releases of IPC shared memory. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> CC: 18.0 18.1 <[email protected]> (cherry picked from commit f56e22e49673e8234a7fe0c241b4c3eae4752f34)
* st/omx/enc: fix blit setup for YUV LoadImageLeo Liu2018-04-301-4/+4
| | | | | | | | | | | | | | | | | | The blit here involves scaling since it's copying from I8 format to R8G8 format. Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it looks that GPU always uses the second half as source. Currently we use "1" as the start point of x for R, then causing 1 source pixel of U component shift to right. So "-1" should be the start point for U component. Cc: 18.0 18.1 <[email protected]> Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 1c5f4f4e17f74d823d9e38c678e40e9f49e2c053) [Juan A. Suarez: apply patch in src/gallium/state_trackers/omx_bellagio/vid_enc.c] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/gallium/state_trackers/omx/vid_enc_common.c
* gallium/util: Fix incorrect refcounting of separate stencil.Eric Anholt2018-04-301-2/+1
| | | | | | | | | | | | The driver may have a reference on the separate stencil buffer for some reason (like an unflushed job using it), so we can't directly free the resource and should instead just decrement the refcount that we own. Fixes double-free in KHR-GLES3.packed_depth_stencil.blit.depth32f_stencil8 on vc5. Fixes: e94eb5e6000e ("gallium/util: add u_transfer_helper") Reviewed-by: Rob Clark <[email protected]> (cherry picked from commit 069c409f434ab215940aad2092d5d236b410a7b9)
* radeonsi/gfx9: workaround for INTERP with indirect indexingMarek Olšák2018-04-301-6/+13
| | | | | | | | and clean up the conditions. Reviewed-by: Nicolai Hähnle <[email protected]> Cc: 18.0 18.1 <[email protected]> (cherry picked from commit 6d19120da851c0d3f97376c733d674f7c8ab0457)
* util/u_queue: fix a deadlock in util_queue_finishMarek Olšák2018-04-302-0/+10
| | | | | | Cc: 18.0 18.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 7083ac7290a0c37a45494437a45441112f3cc36c)
* anv/allocator: Don't shrink either end of the block poolJason Ekstrand2018-04-301-4/+4
| | | | | | | | | | | | | | Previously, we only tried to ensure that we didn't shrink either end below what was already handed out. However, due to the way we handle relocations with block pools, we can't shrink the back end at all. It's probably best to not shrink in either direction. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105374 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106147 Tested-by: Eero Tamminen <[email protected]> Reviewed-by: Scott D Phillips <[email protected]> Cc: [email protected] (cherry picked from commit 3db93f9128e5329f6658c9018cf23eb31807c24c)
* meson: don't build classic mesa tests without dri_driversDylan Baker2018-04-251-1/+1
| | | | | | | | | | | Since mesa_classic is build-on-demand the tests will create a demand and add a bunch of extra compilation. Fixes: 43a6e84927e3b1290f6f211f5dfb184dfe5a719e ("meson: build mesa test.") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit aaab6242456a4a5e737da0add179704b0b6f3676)
* radv/winsys: allow to submit up to 4 IBs for chips without chainingSamuel Pitoiset2018-04-251-50/+169
| | | | | | | | | | | | | | | | | | | The SI family doesn't support chaining which means the maximum size in dwords per CS is limited. When that limit was reached we failed to submit the CS and the application crashed. This patch allows to submit up to 4 IBs which is currently the limit, but recent amdgpu supports more than that. Please note that we can reach the limit of 4 IBs per submit but currently we can't improve that. The only solution is to upgrade libdrm. That will be improved later but for now this should fix crashes on SI or when using RADV_DEBUG=noibs. Fixes: 36cb5508e89 ("radv/winsys: Fail early on overgrown cs.") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105775 Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]>
* intel/compiler: Add scheduler deps for instructions that implicitly read g0Ian Romanick2018-04-252-0/+28
| | | | | | | | | | | | | | Otherwise the scheduler can move the writes after the reads. Signed-off-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95009 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95012 Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Mark Janes <[email protected]> Cc: Clayton A Craft <[email protected]> Cc: [email protected] (cherry picked from commit 0d5ce25c1ca23abc6d91538f4374a18509091060)
* Revert "st/dri: Fix dangling pointer to a destroyed dri_drawable"Marek Olšák2018-04-241-4/+0
| | | | | | | | | | | This reverts commit dab02dea3411d325a5aee6cda5b581e61396ecc6. It causes crashes of qtcreator and firefox. Fixes: dab02de "st/dri: Fix dangling pointer to a destroyed dri_drawable" Cc: 18.0 18.1 <[email protected]> (cherry picked from commit 4559aefb5cee5878198f8491680abe47df3e3250)
* i965/fs: Return mlen * 8 for size_read() for INTERPOLATE_AT_*Jason Ekstrand2018-04-241-0/+2
| | | | | | | | | | They are send messages and this makes size_read() and mlen agree. For both of these opcodes, the payload is just a dummy so mlen == 1 and this should decrease register pressure a bit. Reviewed-by: Francisco Jerez <[email protected]> Cc: [email protected] (cherry picked from commit de1f22d595d40f6c2e2d80db73aa90d62a875de5)
* st/dri: Fix dangling pointer to a destroyed dri_drawableJohan Klokkhammer Helsing2018-04-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | If an EGLSurface is created, made current and destroyed, and then a second EGLSurface is created. Then the second malloc in driCreateNewDrawable may return the same pointer address the first surface's drawable had. Consequently, when dri_make_current later tries to determine if it should update the texture_stamp it compares the surface's drawable pointer against the drawable in the last call to dri_make_current and assumes it's the same surface (which it isn't). When texture_stamp is left unset, then dri_st_framebuffer_validate thinks it has already called update_drawable_info for that drawable, leaving it unvalidated and this is when bad things starts to happen. In my case it manifested itself by the width and height of the surface being unset. This is fixed this by setting the pointer to NULL before freeing the surface. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106126 Signed-off-by: Johan Klokkhammer Helsing <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Cc: 18.0 18.1 <[email protected]> (cherry picked from commit dab02dea3411d325a5aee6cda5b581e61396ecc6)
* etnaviv: fix texture_format_needs_swizLucas Stach2018-04-231-1/+1
| | | | | | | | | | | | | | memcmp returns 0 when both swizzles are the same, which means we don't need any hardware swizzling. texture_format_needs_swiz should return true when the return value of the memcmp is non-zero. Fixes: 751ae6afbefd ("etnaviv: add support for swizzled texture formats") Cc: [email protected] Signed-off-by: Lucas Stach <[email protected]> Tested-by: Marek Vasut <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> (cherry picked from commit 52e93e309f34972dfd5b84075c13ae8d6b9f63df)
* radv: Mark GTT memory as device local for APUs.Bas Nieuwenhuizen2018-04-231-3/+5
| | | | | | | | | Otherwise a lot of games complain about not having enough memory, and it is sort of local so this seems reasonable to me. CC: 18.0 <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit e1df849c3cfe0c9da7d2f62fc78be94632949903)
* i965: Fix shadow batches to be the same size as the real BO.Kenneth Graunke2018-04-231-1/+4
| | | | | | | | | | | | | | | brw_bo_alloc may round up our allocation size to the next bucket size. In this case, we would malloc a shadow buffer that was the original intended size, but use bo->size (the larger size) for all of our checks. This could cause us to run off the end of the shadow buffer. v2: Actually use the new BO size (caught by Lionel) Reported-by: James Xiong <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Fixes: c7dcee58b5fe183e1653c13bff6a212f0d157b29 (i965: Avoid problems from referencing orphaned BOs after growing.) (cherry picked from commit da25ae92bebb8921003c0df30820d06a5f5e3fef)
* radv: fix scissor computation when using half-pixel viewport offsetSamuel Pitoiset2018-04-231-4/+4
| | | | | | | | | | | | 'scale[i]' can be non-integer. Original patch by Philip Rebohle. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106074 Fixes: 0f3de89a56a ("radv: Use the guard band.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Niuwenhuizen <[email protected]> (cherry picked from commit 893e19efb74edd6133a607e09338bf5d449632f1)
* anv: fix number of planes for depth & stencilLionel Landwerlin2018-04-232-1/+5
| | | | | | | | | | | | | | | | We're not counting correctly with depth & stencil images. Additionally we need to move an assert that is meant just for color attachments. v2: Move an assert() (Reported by Craig) Change aspect mask checks (Francesco) Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: a62a97933578a ("anv: enable multiple planes per image/imageView") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105994 Reviewed-by: Nanley Chery <[email protected]> (cherry picked from commit 0a6547014fbe5371f5b7253f2c2640ad0026b184)
* mesa: free debug messages when destroying the debug stateTimothy Arceri2018-04-231-22/+23
| | | | | | | | Fixes: 04a8baad3721 "mesa: refactor _mesa_PopDebugGroup and _mesa_free_errors_data" Reviewed-by: Iago Toral Quiroga <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98281 (cherry picked from commit a63e69f5f0b4d960bd106068d8c7d13b82fea759)
* svga: Fix incorrect advertizing of EGL_KHR_gl_colorspaceThomas Hellstrom2018-04-231-1/+1
| | | | | | | | | | | | | | | | | | | | When advertizing this extension, egl_dri2 uses the DRI2_RENDERER_QUERY extension to query whether an sRGB format is supported. That extension will query our driver with the BIND flag PIPE_BIND_RENDER_TARGET rather than PIPE_BIND_DISPLAY_TARGET which is used when building the configs. We only return the correct value for PIPE_BIND_DISPLAY_TARGET. The inconsistency causes EGL to crash at surface initialization if sRGB is not supported. Fix this by supporting both bind flags. Testing done: piglit egl_gl_colorspace srgb Cc: <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> (cherry picked from commit e0c08183fb20399128ff363467e00aa1e8767886)
* glsl_to_tgsi: try harder to lower unsupported ir_binop_vector_extractMarek Olšák2018-04-231-0/+5
| | | | | | | | This fixes some piglits. Cc: 18.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit 7bd24d951a69292b5a8090000541ece2142591ef)
* radeonsi/gfx9: fix a hang with an empty first IBMarek Olšák2018-04-231-3/+6
| | | | | | | | This packet causes the no-op IB detection to fail, so the IB is always submitted. Also fix the no-op IB detection by moving the begin call. Cc: 18.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* ac/nir: Make the GFX9 buffer size fix apply to image loads/atomics too.Bas Nieuwenhuizen2018-04-231-17/+22
| | | | | | | | | | | | | | | No clue how I missed those ... Fixes: 4503ff760c "ac/nir: Add workaround for GFX9 buffer views." CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105320 Reviewed-by: Nicolai Hähnle <[email protected]> (cherry picked from commit b0e3a9b19f16ed1ce4c1f150718b0c0f0e6111f6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/common/ac_nir_to_llvm.c
* st/va: Enable vaExportSurfaceHandle()Mark Thompson2018-04-172-2/+8
| | | | | | | | It is present from libva 2.1 (VAAPI 1.1.0 or higher). Signed-off-by: Mark Thompson <[email protected]> Reviewed-by: Christian König <[email protected]> (cherry picked from commit 768f1487b0c084507ba5e2641e0bbf4ec789ec85)
* radv: fix radv_layout_dcc_compressed() when image doesn't have DCCSamuel Pitoiset2018-04-121-1/+1
| | | | | | | | | | | | | | | | | | | num_dcc_levels means that DCC is supported, but this doesn't mean that it's enabled by the driver. Instead, we should rely on radv_image_has_dcc(). This fixes some multisample regressions since 0babc8e5d66 ("radv: fix picking the method for resolve subpass") on Vega. This is because the resolve method changed from HW to FS, but those fails are totally unexpected, so there might some differences between Polaris and Vega here. Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute transfer dest.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 9eac49246cdc501530418e8bd2a3e6d47173332b) [Juan A. Suarez: do not call radv_image_has_dcc(), as it is not defined] Signed-off-by: Juan A. Suarez Romero <[email protected]>
* radv: fix picking the method for resolve subpassSamuel Pitoiset2018-04-121-1/+1
| | | | | | | | | | | | The source and destination image parameters were swapped. No CTS changes on Polaris10, but I suspect this might fix something. Fixes: 2a04f5481df ("radv/meta: select resolve paths") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 0babc8e5d665e54783c926b89183ab9a596aa04c)
* radv: Always reset draw user SGPRs after secondary command buffer.Bas Nieuwenhuizen2018-04-121-14/+3
| | | | | | | | | As we sometimes reset them to -1, -1 does not mean that they are not written by the secondary command buffer. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 41fbcc7901bc7a95fb7d5ccffdb3c18ba0361c40)
* radv: Don't set instance count using predication.Bas Nieuwenhuizen2018-04-121-1/+1
| | | | | | | | | | | The packet can sometimes be skipped, but we still think the change takes effect. This just makes the packet always take effect. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 74b0b869ddd4dbd36482aa9bec3403d45396af2d)
* mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usageAndres Gomez2018-04-121-2/+8
| | | | | | | | | | | Fixes: 03fd6704db9 ("mesa: Add support for a new override string MESA_GLES_VERSION_OVERRIDE") Cc: Jordan Justen <[email protected]> Cc: Ian Romanick <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (cherry picked from commit 7cf3932098aba5fefaf241e35ee276b82e6e8ec7)
* mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API overrideMarek Olšák2018-04-121-12/+11
| | | | | | | | | | | | | | | | | | | v2: - Provide a correct explanation on the envvars documentation (Ian). - Provide a more correct explanation on the function comments (Andres). v3: - Homogenize documentation and inline comments (Emil). - Correct a typo (Emil). Fixes: 2599b92eb97 ("mesa: allow forcing >=3.1 compatibility contexts with MESA_GL_VERSION_OVERRIDE") Cc: Jordan Justen <[email protected]> Cc: Ian Romanick <[email protected]> Cc: Eric Engestrom <[email protected]> Cc: Emil Velikov <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (cherry picked from commit 806ab42c0f53064a774f002e311cfbb7ff10a667)
* dri_util: when overriding, always reset the core versionAndres Gomez2018-04-121-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This way we won't fail when validating just because we may have a non overriden core version that is lower than the requested one, even when the compat version is high enough. For example, running glcts from VK-GL-CTS with i965, this will succeed: $ MESA_GL_VERSION_OVERRIDE=4.6 ./glcts --deqp-case=KHR-GL46.info.vendor While, this will fail: $ MESA_GL_VERSION_OVERRIDE=4.6COMPAT ./glcts --deqp-case=KHR-GL46.info.vendor Fixes: 464c56d3d5c ("dri_util: Use _mesa_override_gl_version_contextless") Cc: Ian Romanick <[email protected]> Cc: Tapani Pälli <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> (cherry picked from commit 044acd3569cbe689712be3c35544ceb7da4e5347)
* meson: Set .so version for xa like autotools doesDylan Baker2018-04-121-1/+3
| | | | | | | | | Fixes: 0ba909f0f111824223bc38563d1a6bc73e69c2cc ("meson: build gallium xa state tracker") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (cherry picked from commit 19dbed6477525bff2918182b06bf01314f3cd5e9)
* nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destinationJason Ekstrand2018-04-121-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise we may end up trying to coalesce in a case such as ssa_1 = fadd r1, r2 r3.x = fneg(r2); r3 = vec4(ssa_1, ssa_1.y, ...) and that would cause us to move the writes to r3 from the vec to the fadd which would re-order them with respect to the write from the fneg. In order to solve this, we just don't coalesce if the destination of the vec is not SSA. We could try to get clever and still coalesce if there are no writes to the destination of the vec between the vec and the ALU source. However, since registers only come from phi webs and indirects, the chances of having a vec with a register destination that is actually coalescable into its source is very slim. Shader-db results on Haswell: total instructions in shared programs: 13657906 -> 13659101 (<.01%) instructions in affected programs: 149291 -> 150486 (0.80%) helped: 0 HURT: 592 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440 Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when possible" Reported-by: Vadym Shovkoplias <[email protected]> Tested-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit 800df942eadc5356840f5cbc2ceaa8a65c01ee91)
* glsl: always call do_lower_jumps() after loop unrollingTimothy Arceri2018-04-121-0/+18
| | | | | | | | | | | | | | | This fixes a bug in radeonsi where LLVM cannot handle the case where a break exists but its not the last instruction in the block. LLVM would fail with: Terminator found in the middle of a basic block! LLVM ERROR: Broken function found, compilation aborted! Fixes: 96fe8834f539 "glsl_to_tgsi: do fewer optimizations with GLSLOptimizeConservatively" Reviewed-by: Matt Turner <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105317 (cherry picked from commit b42633db8e3711e54a5bd10495b1436b8e362801)
* gallium/pipebuffer: fix parenthesis locationTimothy Arceri2018-04-121-1/+1
| | | | | | | | | | | Without this the return value will never get set to -1. This was first added in 49866c8f3457 and copied in 2b396eeed983. Fixes: 2b396eeed983 "gallium/pb_cache: add a copy of cache bufmgr independent of pb_manager" Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102342 (cherry picked from commit 7e9b7ec094500f1245eed518592f99244e54a753)
* st/dri: Initialise modifier to INVALID for DRI2Daniel Stone2018-04-121-0/+1
| | | | | | | | | | | | | | | | When allocating a buffer for DRI2, set the modifier to INVALID to inform the backend that we have no supplied modifiers and it should do its own thing. The missed initialisation forced linear, even if the implementation had made other decisions. This resulted in VC4 DRI2 clients failing with: Modifier 0x0 vs. tiling (0x700000000000001) mismatch Signed-off-by: Daniel Stone <[email protected]> Reported-by: Andreas Müller <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Fixes: 3f8513172ff6 ("gallium/winsys/drm: introduce modifier field to winsys_handle") (cherry picked from commit 4cbecb61682a0ee426faaa03d824fc8fd7aef826)
* intel/vec4: Set channel_sizes for MOV_INDIRECT sourcesJason Ekstrand2018-04-121-1/+4
| | | | | | | | | | | | Otherwise, any indirect push constant access results in an assertion failure when we start digging through the channel_sizes array. This fixes dEQP-VK.pipeline.push_constant.graphics_pipeline.dynamic_index_vert on Haswell. It should be a harmless no-op for GL since indirect push constants aren't used there. Reviewed-by: Kenneth Graunke <[email protected]> Fixes: e69e5c7006d "i965/vec4: load dvec3/4 uniforms first in the..." (cherry picked from commit 2b977989f3f01c186677988494bbf9b7342b31f2)
* ac/nir: Add workaround for GFX9 buffer views.Bas Nieuwenhuizen2018-04-124-6/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct fix is most likely to disable the LLVM optimization, but we need something to work with LLVM <= 6.0. radeonsi does the max between stride and element count on the CPU but that results in the size intrinsics returning the wrong size for the buffer. This would cause CTS errors for radv. v2: Also include the store changes. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 4503ff760c794c3bb15b978a47c530037d56498e) [Juan A. Suarez: partially backported from 908a0cd1dbe5, a backport for 17.3 stable branch; resolved trivial conflicts] Conflicts: src/amd/common/ac_nir_to_llvm.c src/amd/vulkan/radv_nir_to_llvm.c
* gbm: remove never-implemented functionEric Engestrom2018-04-122-3/+0
| | | | | | | | | | | I assume this was implemented in a previous version of that commit, but was removed in the version that actually landed. Fixes: 8430af5ebe1ee8119e14 "Add support for swrast to the DRM EGL platform" Cc: Giovanni Campagna <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (cherry picked from commit 431a1d12cc48060366caf49da76108cd0406b0f6)
* nir: fix crash in loop unroll corner caseTimothy Arceri2018-04-121-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an if nesting inside anouther if is optimised away we can end up with a loop terminator and following block that looks like this: if ssa_596 { block block_5: /* preds: block_4 */ vec1 32 ssa_601 = load_const (0xffffffff /* -nan */) break /* succs: block_8 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 */ } block block_7: /* preds: block_6 */ vec1 32 ssa_602 = phi block_6: ssa_552 vec1 32 ssa_603 = phi block_6: ssa_553 vec1 32 ssa_604 = iadd ssa_551, ssa_66 The problem is the phis. Loop unrolling expects the last block in the loop to be empty once we splice the instructions in the last block into the continue branch. The problem is we cant move phis so here we lower the phis to regs when preparing the loop for unrolling. As it could be possible to have multiple additional blocks/ifs following the terminator we just convert all phis at the top level of the loop body for simplicity. We also add some comments to loop_prepare_for_unroll() while we are here. Fixes: 51daccb289eb "nir: add a loop unrolling pass" Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670 (cherry picked from commit 629ee690addad9b3dc8f68cfff5ae09858f31caf)
* glsl: fix infinite loop caused by bug in loop unrolling passTimothy Arceri2018-04-121-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Just checking for 2 jumps is not enough to be sure we can do a complex loop unroll. We need to make sure we also have also found 2 loop terminators. Without this we were attempting to unroll a loop where the second jump was nested inside multiple ifs which loop analysis is unable to detect as a terminator. We ended up splicing out the first terminator but failed to actually unroll the loop, this resulted in the creation of a possible infinite loop. Fixes: 646621c66da9 "glsl: make loop unrolling more like the nir unrolling path" Tested-by: Gert Wollny <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670 (cherry picked from commit 56b867395dee1a48594b27987d3bf68a4e745dda) Squashed with: glsl: remove unreachable assert() Earlier commit enforced that we'll bail out if the number of terminators is different than 2. With that in mind, the assert() will never trigger. Fixes: 56b867395de ("glsl: fix infinite loop caused by bug in loop unrolling pass") Reviewed-by: Timothy Arceri <[email protected]> Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 8eceac9de7d3cd4fddabbe61d512acfed9812169)
* i965/perf: fix config registration when uploading to kernelLionel Landwerlin2018-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | When registring configurations to the kernel for the first time, we run into an issue where the id number is not properly set (we're using the wrong variable). As a result when trying to use that id later on, we get an error. This issue manifest itself the first time you use frameretrace after reboot, subsequent runs are fine. Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit 1603ce1921a511f128025a49d055283440376231) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/mesa/drivers/dri/i965/brw_performance_query.c
* anv/pipeline: fail if TCS/TES compile failCaio Marcelo de Oliveira Filho2018-04-121-7/+9
| | | | | | | | v2: Add Fixes tag. (Lionel) Fixes: e50d4807a35e679 ("anv: Compile TCS/TES shaders.") Reviewed-by: Lionel Landwerlin <[email protected]> (cherry picked from commit 318073ce660ca72b47ba83e37d1d0bc756f779b7)
* ac: make use of if/loop build helpersTimothy Arceri2018-04-121-42/+18
| | | | | | | | | | | | | These helpers insert the basic block in the same order as they appear in NIR making it easier to follow LLVM IR dumps. The helpers also insert more useful labels onto the blocks. TGSI use the line number of the corresponding opcode in the TGSI dump as the label id, here we use the corresponding block index from NIR. Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 99cdc019bf6fe11c135b7544ef6daf4ac964fa24)
* radeonsi: make use of if/loop build helpers in acTimothy Arceri2018-04-122-160/+11
| | | | | Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 6e1a142863b368a032e333f09feb107241446053)
* ac: add if/loop build helpersTimothy Arceri2018-04-123-0/+212
| | | | | | | | | | | | | These have been ported over from radeonsi. Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit 42627dabb4db3011825a022325be7ae9b51103d6) [Juan A. Suarez: resolve trivial conflicts] Signed-off-by: Juan A. Suarez Romero <[email protected]> Conflicts: src/amd/common/ac_llvm_build.c src/amd/common/ac_llvm_build.h
* egl/wayland: Make swrast display_sync the correct queueDerek Foreman2018-04-121-1/+1
| | | | | | | | | | | | | | | commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface queues, but the display_sync for swrast_commit_backbuffer remained on the old queue. This is likely to break when dispatching the correct queue at the top of function (which can't dispatch the sync callback we're waiting for). The easiest known reproduction case is running weston-subsurfaces under weston --use-pixman Signed-off-by: Derek Foreman <[email protected]> Reviewed-by: Daniel Stone <[email protected]> (cherry picked from commit aa18a63512ccfa4eb8bc5d043e8967738a465af4)
* i965: return the fourcc saved in __DRIimage when possibleXiong, James2018-04-121-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating a image from a texture, the image's dri_format is set to the first plane's format, and used to look up for the fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to __DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function intel_lookup_fourcc(): { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, instead of the correct one: { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned. To fix this bug, the image inherits the texture's planar_format that has the original fourcc; Upon querying, if planar_format is set, return the saved fourcc; Otherwise fall back to the old way. v3: add a bug description and "cc mesa-stable" tag (Jason) remove redundant null pointer check (Tapani) squash 2 patches into one (James) v2: fall back to intel_lookup_fourcc() when planar_format is NULL (Dongwon & Matt Roper) Cc: [email protected] Signed-off-by: Xiong, James <[email protected]> Reviewed-by: Tapani Pälli <[email protected]> (cherry picked from commit f23b45dce3888112b7d26a623ab1280ce86533a1)
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