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* nir: Add a read_mask helper for ALU instructionsJason Ekstrand2018-11-082-7/+14
* intel/fs: Use the new nir_src_is_const and friendsJason Ekstrand2018-11-081-110/+87
* intel/fs,vec4: Clean up a repeated pattern with SSBOsJason Ekstrand2018-11-084-166/+85
* radv: fix GPU hangs when loading depth/stencil clear values on SI/CIKSamuel Pitoiset2018-11-081-5/+19
* radv: use LOAD_CONTEXT_REG when loading fast clear valuesSamuel Pitoiset2018-11-082-19/+27
* radv: only expose VK_SUBGROUP_FEATURE_ARITHMETIC_BIT for VI+Samuel Pitoiset2018-11-081-1/+1
* glx: Demand success from CreateContext requests (v2)Adam Jackson2018-11-071-38/+55
* gm107/ir: fix compile time warning in getTEXSMaskKarol Herbst2018-11-071-0/+1
* winsys/amdgpu: Stop using amdgpu_bo_handle_type_kms_noimportMichel Dänzer2018-11-071-3/+3
* intel/dump_gpu: add platform optionLionel Landwerlin2018-11-072-6/+29
* intel/dump_gpu: move output option togetherLionel Landwerlin2018-11-071-5/+5
* radv: disable conditional rendering for vkCmdCopyQueryPoolResults()Samuel Pitoiset2018-11-071-0/+10
* radv: allocate enough space in CS when copying query results with computeSamuel Pitoiset2018-11-071-0/+4
* ac/nir_to_llvm: fix b2f for f64Timothy Arceri2018-11-071-3/+12
* gm107/ir: use scalar tex instructions where possibleKarol Herbst2018-11-062-3/+317
* nv50/ir: add scalar field to TexInstructionsKarol Herbst2018-11-062-1/+6
* nv50/ra: add condenseDef overloads for partial condensesKarol Herbst2018-11-061-8/+21
* nv50/ir: print color masks of tex instructionsKarol Herbst2018-11-061-4/+33
* vulkan: Update the XML and headers to 1.1.91Jason Ekstrand2018-11-061-220/+243
* r600: Add support for EXT_texture_sRGB_R8Gert Wollny2018-11-061-0/+1
* anv/android: mark gralloc allocated BOs as externalLionel Landwerlin2018-11-061-1/+1
* anv: stub internal android codeLionel Landwerlin2018-11-067-11/+80
* freedreno/a6xx: Clear z32 and separate stencil with blitterKristian H. Kristensen2018-11-062-27/+50
* freedreno/a6xx: fix VSC bug with larger # of tilesRob Clark2018-11-061-5/+2
* freedreno: update generated headersRob Clark2018-11-067-29/+51
* wayland/egl: Resize EGL surface on update buffer for swrastOlivier Fourdan2018-11-061-2/+2
* intel/decoders: fix instruction base address parsingLionel Landwerlin2018-11-052-2/+2
* egl/glvnd: correctly report errors when vendor cannot be foundEmil Velikov2018-11-051-0/+5
* egl: add EGL_EXT_device_base entrypointsEmil Velikov2018-11-051-0/+7
* st/va: fix incorrect use of resource_destroyMarek Olšák2018-11-051-4/+2
* i965/batch/debug: Allow log be dumped before assertSergii Romantsov2018-11-051-1/+1
* intel/sanitize_gpu: add debug message on mmap failLionel Landwerlin2018-11-051-1/+3
* intel/sanitize_gpu: deal with non page multiple buffer sizesLionel Landwerlin2018-11-051-4/+7
* intel/sanitize_gpu: add help/gdb options to wrapperLionel Landwerlin2018-11-051-1/+54
* intel/dump_gpu: add missing gdb optionLionel Landwerlin2018-11-051-0/+2
* wsi/wayland: only finish() a successfully init()ed displayEric Engestrom2018-11-051-1/+2
* wsi/wayland: use proper VkResult typeEric Engestrom2018-11-051-2/+2
* autotools: library-dependency when no sse and 32-bitSergii Romantsov2018-11-052-2/+3
* radv: more use of radv_cp_wait_mem()Samuel Pitoiset2018-11-051-22/+9
* radv: replace si_emit_wait_fence() with radv_cp_wait_mem()Samuel Pitoiset2018-11-054-10/+14
* radv: add missing TFB queries support to CmdCopyQueryPoolsResults()Samuel Pitoiset2018-11-052-0/+278
* radv: remove useless sync after copying query results with computeSamuel Pitoiset2018-11-051-4/+0
* r600/sb: Fix constant logical operand in assert.Vinson Lee2018-11-041-1/+1
* st/mesa: Don't record garbage streamout information in the non-SSO case.Kenneth Graunke2018-11-033-31/+15
* st/nir: Drop unused parameter from st_nir_assign_uniform_locations().Kenneth Graunke2018-11-031-2/+1
* st/mesa: Pull nir_lower_wpos_ytransform work into a helper function.Kenneth Graunke2018-11-032-29/+40
* intel: Use a URB start offset of 0 for disabled stages.Kenneth Graunke2018-11-031-3/+9
* android: radv: add libmesa_git_sha1 static dependencyMauro Rossi2018-11-031-1/+2
* vc4: Use the normal simulator ioctl path for CL submit as well.Eric Anholt2018-11-023-13/+5
* vc4: Maintain a separate GEM mapping of BOs in the simulator.Eric Anholt2018-11-022-42/+58
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