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* i965/fs: Initial plumbing to support TXD.Kenneth Graunke2011-02-252-0/+14
| | | | | This adds the opcode and the code to convert ir_txd to OPCODE_TXD; it doesn't actually add support yet.
* i965/fs: Complete TXL support on gen5+.Kenneth Graunke2011-02-251-0/+7
| | | | | Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
* i965/fs: Complete TXL support on gen4.Kenneth Graunke2011-02-251-0/+10
| | | | | Initial plumbing existed to turn the ir_txl into OPCODE_TXL, but it was never handled.
* i965/fs: Use a properly named constant in TXB handling.Kenneth Graunke2011-02-251-1/+1
| | | | | | | The old value, BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE makes it sound like we're doing a non-bias texture lookup. It has the same value as the new constant BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE, so there should be no functional changes.
* i965: Add #defines for gen4 SIMD8 TXB/TXL with shadow comparison.Kenneth Graunke2011-02-251-0/+2
| | | | From volume 4, page 161 of the public i965 documentation.
* gallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issueJerome Glisse2011-02-251-14/+14
| | | | | | | | | | | | There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa due to ureg_src size, reshuffling the structure member to better better alignment work around the issue. http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893 7.9 + 7.10 candidate Signed-off-by: Jerome Glisse <[email protected]>
* gallium/st: place value check before value is useJerome Glisse2011-02-251-1/+1
| | | | | | 7.9 & 7.10 candidate Signed-off-by: Jerome Glisse <[email protected]>
* gallium/util: add 1d/2d mipmap generation supportDave Airlie2011-02-251-6/+37
| | | | | | | | so far only hw mipmap generation is testing on softpipe, passes test added to piglit. this requires another patch to mesa to let array textures mipmaps even start to happen.
* scons: Reduce all Cygwin platform names to 'cygwin'.Vinson Lee2011-02-241-1/+1
| | | | | | | | | | | platform.system in SCons on Cygwin includes the OS version number. Windows XP - CYGWIN_NT-5.1 Windows Vista - CYGWIN_NT-6.0 Windows 7 - CYGWIN_NT-6.1 Reduce all Cygwin platform variants to just 'cygwin' so anything downstream can simply use 'cygwin' instead of the different full platform names.
* r600g: explicity set sign bits for RGTCDave Airlie2011-02-251-2/+4
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* r600g: bc 4/5 or rgtc textures need to be tiled as well.Dave Airlie2011-02-252-10/+10
| | | | | | Make the s3tc upload code more generic. Signed-off-by: Dave Airlie <[email protected]>
* r300g: explicit sign bits on RGTC texturesDave Airlie2011-02-251-2/+4
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* i965: Increase Sandybridge point size clamp in the clip state.Kenneth Graunke2011-02-241-1/+1
| | | | | | | | | 255.875 matches the hardware documentation. Presumably this was a typo. NOTE: This is a candidate for the 7.10 branch, along with commit 2bfc23fb86964e4153f57f2a56248760f6066033. Reviewed-by: Eric Anholt <[email protected]>
* intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebufferNeil Roberts2011-02-243-22/+108
| | | | | | | | | | | | | | | | In the case where glBlitFramebuffer is being used to copy to a texture without scaling it is faster if we can use the hardware to do a blit rather than having to do a texture render. In most of the drivers glCopyTexSubImage2D will use a blit so this patch makes it check for when glBlitFramebuffer is doing a simple copy and then divert to glCopyTexSubImage2D. This was originally proposed as an extension to the common meta-ops. However, it was rejected as using the BLT is only advantageous for Intel hardware. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934 Signed-off-by: Chris Wilson <[email protected]>
* nvc0: fix PointCoord enable in FP headerChristoph Bumiller2011-02-241-2/+5
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* nvc0: change TGSI CMP translation to use slctChristoph Bumiller2011-02-243-8/+15
| | | | Saves us the explicit compare instruction needed with selp.
* nvc0: sprite coord enable is per GENERIC, not overall indexChristoph Bumiller2011-02-241-5/+3
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* nvc0: fix new_value calls using type instead of sizeChristoph Bumiller2011-02-241-3/+3
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* nvc0: set local memory usage info in shader headerChristoph Bumiller2011-02-246-3/+34
| | | | Before this, l[] access was a no-op.
* nvc0: don't fold loads from local memoryChristoph Bumiller2011-02-241-0/+5
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* nvc0: presin and preex2 can load from const spaceChristoph Bumiller2011-02-241-2/+2
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* nvc0: kick out empty live rangesChristoph Bumiller2011-02-241-0/+3
| | | | They affect overlap tests even though they're actually empty.
* nvc0: preemptively insert branch at ENDIFChristoph Bumiller2011-02-242-1/+9
| | | | | | | Might be necessary if a block sneaks in somewhere, like a common block for moves of phi sources after a loop break. This is harmless and normally will be removed before emission.
* nvc0: correct allocation of constrained registersChristoph Bumiller2011-02-241-67/+154
| | | | | | | In linear scan we can't allocate multiple values with different live ranges at the same time to assign them consecutive regs. Maybe we should just switch to graph coloring for all values ...
* nvc0: sync textures with render targets ourselvesChristoph Bumiller2011-02-246-6/+35
| | | | Fixes for example piglit/fbo-flushing and nexuiz' bloom effect.
* nvc0: improve userspace fencingChristoph Bumiller2011-02-246-26/+46
| | | | | | Before, there were situations in which we never checked the fences for completion (some loading screens for example) and thus never released memory.
* nvc0: values for undefined outputs must have file GPRChristoph Bumiller2011-02-241-7/+4
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* nvc0: multiply polygon offset units by 2Christoph Bumiller2011-02-241-1/+1
| | | | | Wasn't sure if this still was necessary because the piglit test started to fail at some point on nv50 where we already do this.
* nvc0: fix SSGChristoph Bumiller2011-02-241-5/+5
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* nvc0: don't visit target blocks of a loop break multiple timesChristoph Bumiller2011-02-241-1/+4
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* nvc0: don't overwrite phi sources at the end of a loopChristoph Bumiller2011-02-241-1/+5
| | | | Except the reference to its own result.
* gallium/utils: Fix vertex element setupFabian Bieler2011-02-241-2/+3
| | | | Check if element was translated per element instead of per buffer.
* svga: Ensure rendertargets and textures are always rebound at every command ↵José Fonseca2011-02-244-9/+138
| | | | | | | | buffer start. The svga_update_state() mechanism is inadequate as it will always end up flushing the primitives before processing the SVGA_NEW_COMMAND_BUFFER dirty state flag.
* i965: Remember to pack the constant blend color as floats into the batchChris Wilson2011-02-241-4/+4
| | | | | | | Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597 Signed-off-by: Chris Wilson <[email protected]>
* intel: Reset the buffer offset after releasing reference to packed uploadChris Wilson2011-02-242-58/+77
| | | | | | | Fixes oglc/vbo(basic.bufferdata) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603 Signed-off-by: Chris Wilson <[email protected]>
* i965: Unmap the correct pointer after discontiguous uploadChris Wilson2011-02-241-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes piglit/fbo-depth-sample-compare: ==14722== Invalid free() / delete / delete[] ==14722== at 0x4C240FD: free (vg_replace_malloc.c:366) ==14722== by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd ==14722== at 0x4C244E8: malloc (vg_replace_malloc.c:236) ==14722== by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256) ==14722== by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457) ==14722== by 0x852F975: brw_validate_state (brw_state_upload.c:394) ==14722== by 0x851FA24: brw_draw_prims (brw_draw.c:365) ==14722== by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389) ==14722== by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543) ==14722== by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973) ==14722== by 0x86D6A16: _mesa_set_enable (enable.c:351) ==14722== by 0x42CAD1: render_to_fbo (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42CEE3: piglit_display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) ==14722== by 0x42F508: display (in /home/ickle/git/piglit/bin/fbo-depth-sample-compare) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604 Signed-off-by: Chris Wilson <[email protected]>
* intel: Protect against waiting on a NULL render target boChris Wilson2011-02-241-1/+1
| | | | | | | | | | If we fall back to software rendering due to the render target being absent (GPU hang or other error in creating the named target), then we do not need to nor should we wait upon the results. Reported-by: Magnus Kessler <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656 Signed-off-by: Chris Wilson <[email protected]>
* r600g: EXT_texture_array support.Dave Airlie2011-02-246-9/+39
| | | | | | | | | | | This adds EXT_texture_array support to r600g, it passes the piglit array-texture test but I suspect may not be complete. It currently requires a kernel patch to fix the CS checker to allow these, so you need to use R600_ARRAY_TEXTURE=true for now to enable them. Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: treat 1D ARRAY upload like a depth or 2D array upload.Dave Airlie2011-02-241-0/+12
| | | | | | | | | | | | | This is because the HW doesn't always store a 1D array like a 2D texture, it more likely stores it like 2D texture (i.e. alignments etc). This means we upload each slice separately and let the driver work out where to put it. this might break nvc0 as I can't test it, I have only nv50 here. Signed-off-by: Dave Airlie <[email protected]>
* scons: Fix Cygwin platform names.Vinson Lee2011-02-231-1/+1
| | | | Fixes immediate Python exceptions with SCons on Cygwin.
* i915g: Lazy emit dynamic stateJakob Bornecrantz2011-02-245-40/+36
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* i915g: Lazy emit immediate stateJakob Bornecrantz2011-02-245-55/+59
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* i915g: Disable LIS7 state updates for nowJakob Bornecrantz2011-02-242-1/+5
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* i915g: Clean up in i915_state_immediateJakob Bornecrantz2011-02-241-5/+1
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* i915g: Remove outdated commentJakob Bornecrantz2011-02-241-8/+0
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* i915g: Use dump function in sw winsysJakob Bornecrantz2011-02-241-7/+2
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* i915g: Enable mirror repeat wrap modeJakob Bornecrantz2011-02-243-6/+4
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* i915g: Always set vbo to flush on flushesJakob Bornecrantz2011-02-241-1/+1
| | | | Reported-by Chris Wilson <[email protected]>
* intel: gen3 is particular sensitive to batch sizeChris Wilson2011-02-231-1/+1
| | | | | | | | | | | ... and prefers a small batch whereas gen4+ prefer a large batch to carry more state. Tuning using openarena/padman indicate that a batch size of just 4096 is best for those cases. Bugzilla: https://bugs.freedesktop.org/process_bug.cgi Signed-off-by: Chris Wilson <[email protected]>
* i915: And remember assign the new value to the state reg...Chris Wilson2011-02-231-0/+1
| | | | | | | Fixes regression from 298ebb78de8a6b6edf0aa0fe8d784d00bbc2930e. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34589 Signed-off-by: Chris Wilson <[email protected]>
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