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* broadcom/vc5: Add support for anisotropic filtering.Eric Anholt2017-11-071-0/+9
* broadcom/vc5: Fix mipmap filtering enums.Eric Anholt2017-11-072-8/+32
* broadcom/vc5: Fix height padding of small UIF slices.Eric Anholt2017-11-071-1/+5
* broadcom/vc5: Print the actual offsets in HW for our resource layout debug.Eric Anholt2017-11-071-34/+55
* broadcom/vc5: Set the available VS outputs to match the FS inputs.Eric Anholt2017-11-071-1/+4
* broadcom/vc5: Set the max texture LOD bias.Eric Anholt2017-11-071-1/+1
* broadcom/vc5: Fix translation of stencil ops.Eric Anholt2017-11-072-8/+30
* broadcom/vc5: Move stencil state packing to the CSO.Eric Anholt2017-11-073-27/+47
* broadcom/vc5: Introduce a helper for pre-packing our V3DXX structs.Eric Anholt2017-11-072-165/+155
* broadcom/vc5: Add a cl_emit() variant for merging with a pre-packed struct.Eric Anholt2017-11-072-19/+29
* broadcom/vc5: Skip emitting depth offset while disabled.Eric Anholt2017-11-071-1/+4
* broadcom/vc5: Don't emit stencil config if not doing stencil test.Eric Anholt2017-11-071-1/+2
* broadcom/vc5: Don't emit updated blend factors/funcs while disabled.Eric Anholt2017-11-071-1/+5
* broadcom/vc5: Fix missing enum decode for indexed primitives.Eric Anholt2017-11-071-2/+1
* broadcom/vc5: Drop padding bits from the bottom of the TSDA address.Eric Anholt2017-11-071-1/+1
* broadcom/vc5: Make sure the TMU indirect struct is appropriately aligned.Eric Anholt2017-11-071-0/+2
* broadcom/genxml: Fix decoding of groups with small fields.Kenneth Graunke2017-11-071-2/+4
* broadcom/vc5: Use DEPTH24_STENCIL8 for rendering to depth-only textures.Eric Anholt2017-11-071-1/+1
* anv: Suffix anv-private 'VK' tokens with 'ANV'Chad Versace2017-11-075-31/+31
* anv: Remove unused variable 'gen'Chad Versace2017-11-071-4/+0
* radeonsi: add si_screen::has_ls_vgpr_init_bugMarek Olšák2017-11-074-3/+5
* radeonsi: use ac_create_target_machineMarek Olšák2017-11-073-17/+15
* radeonsi: use ac_get_llvm_processor_nameMarek Olšák2017-11-075-39/+7
* radeonsi/gfx9: don't set gs_table_depthMarek Olšák2017-11-071-2/+4
* radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven onlyMarek Olšák2017-11-071-4/+4
* radeonsi: remove unused field in the PCI ID tableMarek Olšák2017-11-073-3/+3
* mesa: fix deleting the dummy ATI_fsMiklós Máté2017-11-071-1/+4
* gallium: Guard assertions by NDEBUG instead of DEBUGMichel Dänzer2017-11-071-1/+1
* meson: drop GLESv1 .so version back to 1.0.0Eric Engestrom2017-11-071-1/+1
* meson: standardize .so version to major.minor.patchEric Engestrom2017-11-078-7/+8
* ac/nir: for ubo load use correct num_componentsDave Airlie2017-11-071-1/+1
* nir: fix a typoGwan-gyeong Mun2017-11-061-1/+1
* glsl: Allow precision mismatch on dead data with GLSL ES 1.00Tomasz Figa2017-11-061-4/+10
* i965: disable NIR linking on HSW and belowTimothy Arceri2017-11-071-1/+4
* radv: move is_local up to the winsys level.Dave Airlie2017-11-064-3/+6
* radv: wrap cs_add_buffer in an inline. (v2)Dave Airlie2017-11-066-41/+49
* radv: when loading regs no need to add bufferDave Airlie2017-11-061-2/+0
* radv: pre-calculate user_data_0 registers and store in pipelineDave Airlie2017-11-065-52/+55
* i965: Enable flush controlNeil Roberts2017-11-062-1/+21
* drisw: Enable flush control for llvmpipe and softpipeAdam Jackson2017-11-061-0/+1
* gallium: Wire up flush controlAdam Jackson2017-11-063-1/+9
* egl: Implement EGL_KHR_context_flush_controlAdam Jackson2017-11-066-1/+24
* glx: Implement GLX_ARB_context_flush_controlNeil Roberts2017-11-067-9/+62
* dri: Add a flush control extensionNeil Roberts2017-11-062-2/+21
* dri: Change __DriverApiRec::CreateContext to take a struct for attribsNeil Roberts2017-11-0614-131/+152
* intel: Don't flush the old context in intelMakeCurrentNeil Roberts2017-11-062-18/+0
* egl/dri2: Factor out context attribute initializationAdam Jackson2017-11-061-24/+7
* etnaviv: Don't over-pad compressed texturesWladimir J. van der Laan2017-11-061-9/+15
* etnaviv: ASTC texture supportWladimir J. van der Laan2017-11-067-2/+57
* etnaviv: Update from rnndbWladimir J. van der Laan2017-11-0613-320/+1015
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