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* mesa/glthread: pass the function name to _mesa_glthread_restore_dispatchMarek Olšák2018-11-204-5/+8
* gallium/u_tests: fix MSVC build by using old-style zero initializersMarek Olšák2018-11-201-3/+3
* i965: Do NIR shader cloning in the caller.Kenneth Graunke2018-11-2012-21/+17
* i965: Use a 'nir' temporary rather than poking at brw_programKenneth Graunke2018-11-206-22/+25
* gallium/u_tests: add a compute shader test that clears an imageMarek Olšák2018-11-201-0/+77
* ac: handle cast derefsDave Airlie2018-11-211-0/+3
* radv: handle loading from shared pointersDave Airlie2018-11-211-9/+18
* ac: avoid casting pointers on bcsel and storesDave Airlie2018-11-213-3/+14
* meson: Add tests to suitesDylan Baker2018-11-2024-33/+70
* i965/batch: avoid reverting batch buffer if saved state is an emptyAndrii Simiklit2018-11-205-2/+13
* glx: make xf86vidmode mandatory for direct renderingEmil Velikov2018-11-204-20/+3
* ac/nir: fix intrinsic name string size in visit_image_atomic()Samuel Pitoiset2018-11-201-1/+1
* radv: Use structured intrinsics instead of indexing workaround for GFX9.Bas Nieuwenhuizen2018-11-193-8/+75
* i965: Allow only one slot of clip distances to be set on Gen4-5.Kenneth Graunke2018-11-191-1/+3
* nir: Make nir_lower_clip_vs optionally work with variables.Kenneth Graunke2018-11-195-15/+40
* nir: Save nir_variable pointers in nir_lower_clip_vs rather than locs.Kenneth Graunke2018-11-191-16/+8
* nir: Inline lower_clip_vs() into nir_lower_clip_vs().Kenneth Graunke2018-11-191-41/+32
* nir: Use nir_shader_get_entrypoint in nir_lower_clip_vs().Kenneth Graunke2018-11-191-4/+2
* nir: handle shared pointers in lowering indirect derefs.Dave Airlie2018-11-201-2/+2
* nir: move getting deref from var after we check deref type.Dave Airlie2018-11-201-4/+3
* spirv/vtn: handle variable pointers without offset loweringDave Airlie2018-11-202-8/+10
* intel/fs,vec4: Fix a compiler warningJason Ekstrand2018-11-192-3/+3
* intel,nir: Move gl_LocalInvocationID lowering to nir_lower_system_valuesJason Ekstrand2018-11-194-34/+50
* gbm: add missing comma between stringsEric Engestrom2018-11-191-1/+1
* radv: implement fast HTILE clears for depth or stencil only on GFX9Samuel Pitoiset2018-11-192-5/+269
* radv: rewrite the condition that checks allowed depth/stencil valuesSamuel Pitoiset2018-11-191-8/+4
* radv: check allowed fast HTILE clears a bit earlierSamuel Pitoiset2018-11-191-0/+5
* radv: add radv_is_fast_clear_{depth,stencil}_allowed() helpersSamuel Pitoiset2018-11-191-2/+16
* radv: add radv_get_htile_fast_clear_value() helperSamuel Pitoiset2018-11-191-3/+18
* radv: remove unnecessary goto in the fast clear pathsSamuel Pitoiset2018-11-191-28/+24
* radv/winsys: remove the max IBs per submit limit for the sysmem pathSamuel Pitoiset2018-11-191-17/+29
* radv/winsys: remove the max IBs per submit limit for the fallback pathSamuel Pitoiset2018-11-191-48/+55
* etnaviv: use dummy RT buffer when rendering without color bufferLucas Stach2018-11-193-2/+19
* virgl: fix vtest regression since fencing changes.Dave Airlie2018-11-191-0/+1
* radv: always clear the FCE predicate after DCC/FMASK/CMASK decompressionsSamuel Pitoiset2018-11-191-5/+8
* radv: tidy up radv_set_dcc_need_cmask_elim_pred()Samuel Pitoiset2018-11-195-15/+14
* radeonsi: fix an out-of-bounds read reported by ASANNicolai Hähnle2018-11-191-0/+4
* r600: Only set context streamout strides info from the shader that has outputsGert Wollny2018-11-191-3/+9
* i965:use FRAMEBUFFER_UNSUPPORTED instead of FRAMEBUFFER_INCOMPLETE_DIMENSIONSGert Wollny2018-11-191-1/+1
* virgl: Use file descriptor instead of un-allocated objectGert Wollny2018-11-191-1/+1
* i965: Add support for and expose EXT_texture_sRGB_R8Gert Wollny2018-11-192-0/+2
* i965: Force zero swizzles for unused components in GL_RED and GL_RGGert Wollny2018-11-191-0/+4
* i965: be more specific about FBO completeness errorsGert Wollny2018-11-191-19/+23
* i965: Correct L8_UNORM_SRGB table entryGert Wollny2018-11-191-1/+1
* virgl: Clean up fences commitRobert Foss2018-11-184-4/+1
* i915: Delete swizzling detection logic.Kenneth Graunke2018-11-174-31/+0
* nv50/ir/ra: enforce max register requirement, and change spill orderIlia Mirkin2018-11-164-16/+26
* nv50/ir/ra: improve condition for short regs, unify with cond for 16-bitIlia Mirkin2018-11-161-7/+7
* nv50/ir: delete MINMAX instruction that is no longer in the BBIlia Mirkin2018-11-161-1/+1
* egl: Print the actual message to the console from _eglError().Eric Anholt2018-11-161-12/+20
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