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* intel/peephole_ffma: Fix swizzle propagationJason Ekstrand2019-01-111-4/+7
| | | | | | | | | | | | | | | The num_components value passed into get_mul_for_src is used to only compose the parts of the swizzle that we know will be used so we don't compose invalid swizzle components. However, we had a bug where we passed the number of components of the add all the way through. For the given source, we need the number of components read from that source. In the case where we have a narrow add, say 2 components, that is sourced from a chain of wider instructions, we may not compose all the swizzles. All we really need to do is pass through the right number of components at each level. Fixes: 2231cf0ba3a "nir: Fix output swizzle in get_mul_for_src" Reviewed-by: Ian Romanick <[email protected]>
* nir: Allow a non-existent sampler deref in nir_lower_samplers_as_derefKenneth Graunke2019-01-111-19/+21
| | | | | | | | | | | | | | GL_ARB_gl_spirv does not provide a sampler deref for e.g. texelFetch(), so we can't assume that both are present and identical. Simply lower each if it is present. Fixes regressions in GL_ARB_gl_spirv tests since I switched everyone to using this pass. Thanks to Alejandro Piñeiro for catching these. Fixes: f003859f97c nir: Make gl_nir_lower_samplers use gl_nir_lower_samplers_as_deref Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Alejandro Piñeiro <[email protected]>
* egl: remove unused includeEric Engestrom2019-01-111-2/+0
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Emil Velikov <[email protected]>
* egl: add missing includesEric Engestrom2019-01-116-0/+9
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Acked-by: Emil Velikov <[email protected]>
* anv/pipeline_cache: fix incorrect guards for NIR cacheIago Toral Quiroga2019-01-111-2/+3
| | | | | Fixes: f6aa9f718516 'anv/pipeline_cache: Add support for caching NIR' Reviewed-by: Lionel Landwerlin <[email protected]>
* blorp: Pass the batch to lookup/upload_shader instead of contextKenneth Graunke2019-01-107-35/+44
| | | | | | | | | This will allow drivers to pin shader buffers if necessary. i965 and anv do not need to do this today, but iris will. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* blorp: Add blorp_get_surface_address to the driver interface.Kenneth Graunke2019-01-103-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, BLORP expects drivers to provide two functions for dealing with buffers: blorp_emit_reloc and blorp_surface_reloc. Both record a relocation and combine the BO address and offset into a full 64-bit address. Traditionally, blorp_surface_reloc has written that combined address to an implicitly-known buffer where surface states are stored. (In contrast, blorp_emit_reloc returns the value.) The upcoming Iris driver stores surface states in multiple buffers, which makes it impossible for blorp_surface_reloc to write the combined address - it only takes an offset, not the actual buffer to write to. This commit adds a third function, blorp_get_surface_address, which combines and returns an address, which is then passed to ISL's surface state fill functions. Softpin-only drivers can return a real address here and skip writing it in blorp_surface_reloc. Relocation-based drivers are have options. They can simply return 0 from the new function, and continue writing the address from blorp_surface_reloc. Or, they can return a presumed address from blorp_get_surface_address, and have other relocation processing write the real value later. For now, i965 and anv simply return 0. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* docs: fix gallium screen cap docsIlia Mirkin2019-01-101-11/+11
| | | | | | | | | Make sure that the next line starts with spaces so that bullets are maintained throughout, add `` around a few more special tokens, and fix SAMPLE_COUNT_TEXTURE -> SAMPLE_COUNT. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* glsl: Make invariant outputs in ES fragment shader not to cause errorDanylo Piliaiev2019-01-111-1/+1
| | | | | | | | | | | | | | | | | In all GLSL ES versions output variables in fragment shader are allowed to be invariant. From Section 4.6.1 ("The Invariant Qualifier") GLSL ES 1.00 spec: "Only the following variables may be declared as invariant: ... - Built-in special variables output from the fragment shader." From Section 4.6.1 ("The Invariant Qualifier") GLSL ES 3.00 spec: "Only variables output from a shader can be candidates for invariance." Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107842
* anv/pipeline: Cache the pre-lowered NIRJason Ekstrand2019-01-101-10/+39
| | | | | | | | | | | | | | | | This adds a second level of caching for the pre-lowered NIR that's only based off of the shader module, entrypoint and specialization constants. This is enough for spirv_to_nir as well as our first round of lowering and optimization. Caching at this level should allow for faster shader recompiles due to state changes. The NIR caching does not get serialized to disk via either the VkPipelineCache serialization mechanism or the transparent on-disk cache. We could but it's usually not that expensive to fall back to SPIR-V for the odd cache miss especially if it only happens once for several misses and it simplifies the cache. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline_cache: Add support for caching NIRJason Ekstrand2019-01-102-0/+118
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline: Hash shader modules and spec constants separatelyJason Ekstrand2019-01-101-15/+39
| | | | | | | The stuff hashed by anv_pipeline_hash_shader is exactly the inputs to anv_shader_compile_to_nir so it can be used for NIR caching. Reviewed-by: Lionel Landwerlin <[email protected]>
* compiler/types: Serialize/deserialize subpass input types correctlyJason Ekstrand2019-01-101-2/+2
| | | | | | | They have glsl_sampler_dim enum values of 8 and 9 which don't work when you & them with 0x7. Fortunately, we have plenty of bits. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline: Move wpos and input attachment lowering to lower_nirJason Ekstrand2019-01-101-11/+8
| | | | | | | This lets us make anv_pipeline_compile_to_nir take a device instead of a pipeline. Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: Compile fp64 funcs only if we do not have 64-bit hardware supportMatt Turner2019-01-101-1/+1
| | | | Brown bag fix...
* anv/pipeline: Constant fold after apply_pipeline_layoutJason Ekstrand2019-01-102-12/+5
| | | | | | | | | | | | Thanks to the new NIR load_descriptor intrinsic added by the UBO/SSBO lowering series, we weren't getting UBO pushing because the UBO range detection pass couldn't see the constants it needed. This fixes that problem with a quick round of constant folding. Because we're folding we no longer need to go out of our way to generate constants when we lower the vulkan_resource_index intrinsic and we can make it a bit simpler. Reviewed-by: Lionel Landwerlin <[email protected]>
* freedreno/a6xx: fix 3d+tiled layoutRob Clark2019-01-101-34/+52
| | | | | | | | The last round of fixing 3d layer+level layout skipped the tiled case, since tiled texture support was not in place yet. This finishes the job. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: move tile_mode to sampler-view CSORob Clark2019-01-102-7/+7
| | | | | | | | | | | This is known when the CSO is created, so no need to patch it in later. Also, it seems like smaller textures where the first level is small enough to be linear, it seems like we should set linear tile mode. See: dEQP-GLES3.functional.texture.format.unsized.rgb_unsigned_byte_3d_pot Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: separate stencil restore/resolve fixesRob Clark2019-01-101-14/+21
| | | | | | | | | | | | | Previously we'd use format/etc from the primary (z32) buffer for the stencil (s8), due to confusion about rsc vs psurf. Rework this to drop extra arg and push down handling of separate stencil case (and make sure we take the fmt from the right place). This doesn't completely fix separate-stencil, but at least it avoids the GPU scribbling over random other cmdstream buffers and causing a bunch of bogus fails in dEQP. Signed-off-by: Rob Clark <[email protected]>
* freedreno: make cmdstream bo's read-only to GPURob Clark2019-01-102-5/+11
| | | | | | | | | | | | | If nothing else, this will make problems with cmdstream getting blit over with pixels easier to track down (ie. faults when it first happens rather than strange failures later from corrupted cmdstream when a stateobj is later reused). (NOTE this somewhat depends on the kernel supporting the flag, and the iommu implementation. But the worst case is just that the cmdstream ends up writeable as before.) Signed-off-by: Rob Clark <[email protected]>
* etnaviv: fix typo in cflush_all descriptionGuido Günther2019-01-101-1/+1
| | | | | Signed-off-by: Guido Günther <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* radv: remove a few more unnecessary KHR suffixesEric Engestrom2019-01-103-11/+11
| | | | | | Cc: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (v1)
* nir: fix copy-paste error in nir_lower_constant_initializersRhys Perry2019-01-101-2/+2
| | | | | | | | Fixes: 393b59e0772e7bf0426bdf61c740752c4e09dde1 ('nir: Rework nir_lower_constant_initializers() to handle functions') Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl/linker: specify proper direction in location aliasing errorAndres Gomez2019-01-101-5/+10
| | | | | | | | | | | The check for location aliasing was always asuming output variables but this validation is also called for input variables. Fixes: e2abb75b0e4 ("glsl/linker: validate explicit locations for SSO programs") Cc: Iago Toral Quiroga <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/isl: move tiled_memcpy static libs from i965 to islTapani Pälli2019-01-1021-401/+381
| | | | | | | | | | | | | | Patch moves intel_tiled_memcpy[_sse41] libraries to isl, renames some functions and types and makes the required build system changes for meson, automake and Android. No functional changes are introduced. v2: code cleanups, move isl_get_memcpy_type to i965 (Jason) v3: move isl_mem_copy_fn to priv header, cleanups (Jason, Dylan) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Dylan Baker <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Enable 64-bit GLSL extensionsMatt Turner2019-01-091-4/+4
| | | | | | | Now that we have software implementations of ARB_gpu_shader_int64 and ARB_gpu_shader_fp64 we can unconditionally enable these extensions. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Compile fp64 software routines and lower double-opsMatt Turner2019-01-094-23/+133
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Heap-allocate temporary storageMatt Turner2019-01-091-3/+5
| | | | | | | | Shaders containing software implementations of double-precision operations can be very large such that we cannot stack-allocate an array of grf_count*16. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Expand size of the 'nr' fieldMatt Turner2019-01-091-4/+3
| | | | | | | | | | | Shaders containing software implementations of double-precision operations can be very large such that we have more the 2^16 virtual registers during optimization. Move the 'nr' field to the union containing the immediate storage and expand it to 32-bits. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Prevent warnings in the following patchMatt Turner2019-01-0911-36/+38
| | | | | | | | | | The next patch replaces an unsigned bitfield with a plain unsigned, which triggers gcc to begin warning on signed/unsigned comparisons. Keeping this patch separate from the actual move allows bisectablity and generates no additional warnings temporarily. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Rearrange code to avoid future problemsMatt Turner2019-01-091-3/+4
| | | | | | | | A follow on commit will move nr to the same union as the immediate data, so we should assert these invariants before we overwrite the nr field. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Avoid false positive assertionsMatt Turner2019-01-091-6/+6
| | | | | | | | | | | A follow on patch will move the 'nr' field to the union containing the immediate field, so prepare by checking that we're only testing these assertions if the .file is correct. The assertions with != ARF were kind of silly to begin with because the <128 check is specifically only for things in the GRF. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Split 64-bit MOV-indirects if neededMatt Turner2019-01-091-1/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler: Lower 64-bit MOV/SEL operationsMatt Turner2019-01-091-1/+49
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* nir: Unset metadata debug bit if no progress madeMatt Turner2019-01-0922-12/+115
| | | | | | | | | | | | | | | | | | | | | NIR metadata validation verifies that the debug bit was unset (by a call to nir_metadata_preserve) if a NIR optimization pass made progress on the shader. With the expectation that the NIR shader consists of only a single main function, it has been safe to call nir_metadata_preserve() iff progress was made. However, most optimization passes calculate progress per-function and then return the union of those calculations. In the case that an optimization pass makes progress only on a subset of the functions in the shader metadata validation will detect the debug bit is still set on any unchanged functions resulting in a failed assertion. This patch offers a quick solution (short of a larger scale refactoring which I do not wish to undertake as part of this series) that simply unsets the debug bit on unchanged functions. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add lowering support for 64-bit operations to softwareMatt Turner2019-01-092-2/+178
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Create nir_builder in nir_lower_doubles_impl()Matt Turner2019-01-091-17/+19
| | | | | | | We're going to use it more in a future patch, and this avoids a lot of gross code. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add and set info::uses_64bitMatt Turner2019-01-092-0/+10
| | | | | | | | Will be used to communicate that a shader uses 64-bit operations to the concerned lowering passes. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Implement lowering of 64-bit shift operationsMatt Turner2019-01-092-0/+143
| | | | | Reviewed-by: Elie Tournier <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Wire up int64 lowering functionsMatt Turner2019-01-092-3/+127
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add some more int64 lowering helpersJason Ekstrand2019-01-091-0/+227
| | | | | | | | | | | [mattst88]: Found in an old branch of Jason's. Jason implemented: inot, iand, ior, iadd, isub, ineg, iabs, compare, imin, imax, umin, umax Matt implemented: ixor, bcsel, b2i, i2b, i2i8, i2i16, i2i32, i2i64, u2u8, u2u16, u2u32, u2u64, and fixed ilt Reviewed-by: Elie Tournier <[email protected]>
* nir: Tag entrypoint for easy recognition by nir_shader_get_entrypoint()Matt Turner2019-01-097-6/+30
| | | | | | | | We're going to have multiple functions, so nir_shader_get_entrypoint() needs to do something a little smarter. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Rework nir_lower_constant_initializers() to handle functionsMatt Turner2019-01-091-34/+25
| | | | | | Previously it assumed that only a single function (the entrypoint) existed and attempted to lower constant initializers of shader outputs for each function, for instance.
* glsl: Add "built-in" functions to do fp32_to_int64(fp32)Sagar Ghuge2019-01-091-0/+31
| | | | | Reviewed-by: Elie Tournier <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* glsl: Add "built-in" functions to do fp32_to_uint64(fp32)Sagar Ghuge2019-01-091-0/+29
| | | | | Reviewed-by: Elie Tournier <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* glsl: Add "built-in" functions to do fp64_to_int64(fp64)Sagar Ghuge2019-01-091-0/+29
| | | | | Reviewed-by: Elie Tournier <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* glsl: Add utility function to round and pack int64_t valueSagar Ghuge2019-01-091-0/+36
| | | | | Reviewed-by: Elie Tournier <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* glsl: Add "built-in" functions to do fp64_to_uint64(fp64)Sagar Ghuge2019-01-091-0/+27
| | | | | Reviewed-by: Elie Tournier <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* glsl: Add utility function to round and pack uint64_t valueSagar Ghuge2019-01-091-0/+32
| | | | | Reviewed-by: Elie Tournier <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* glsl: Add "built-in" functions to do int64_to_fp32(int64_t)Sagar Ghuge2019-01-091-0/+22
| | | | | Reviewed-by: Elie Tournier <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
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