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* mesa: add EXT_dsa glCompressedMultiTex* functionsPierre-Eric Pelloux-Prayer2019-08-197-12/+285
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: add EXT_dsa glCompressedTex* functions display list supportPierre-Eric Pelloux-Prayer2019-08-191-0/+239
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: add EXT_dsa glCompressedTexture(Sub)Image1D/2D/3D functionsPierre-Eric Pelloux-Prayer2019-08-197-69/+290
| | | | Reviewed-by: Marek Olšák <[email protected]>
* mesa: refactor compressed_tex_sub_image functionPierre-Eric Pelloux-Prayer2019-08-191-101/+115
| | | | | | | | | | Combine compressed_tex_sub_image, compressed_tex_sub_image_error and compressed_tex_sub_image_no_error in a single function. The added "enum tex_mode mode" parameter allows to implement the DSA / non-DSA variants and their error/no_error combination. Reviewed-by: Marek Olšák <[email protected]>
* radv: Add Renoir support.Bas Nieuwenhuizen2019-08-192-3/+6
| | | | | | | | | Took the freedom to enable dfsm even though I don't have benchmark results yet, but it seems Raven-like. Rest is from radeonsi. Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi/nir: always lower ballot masks as 64-bit, codegen handles itMarek Olšák2019-08-1911-24/+38
| | | | | | This fixes KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks. This solution is better, because the IR isn't dependent on wave32.
* radeonsi: remove the unsafemath debug optionMarek Olšák2019-08-194-25/+3
| | | | | | unlikely to be used in the future Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/nir: fix counting shader inputs & outputsMarek Olšák2019-08-191-10/+11
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* radeonsi/nir: fix assertion in si_nir_load_sampler_descMarek Olšák2019-08-191-1/+1
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* radeonsi: clean up si_llvm_context_set_tgsiMarek Olšák2019-08-193-20/+12
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: allocate and resize global_buffers as neededMarek Olšák2019-08-192-5/+24
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi/gfx10: don't set PA_SC_TILE_STEERING_OVERRIDE if CLEAR_STATE sets itMarek Olšák2019-08-191-2/+5
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: don't emit PKT3_CONTEXT_CONTROL on amdgpuMarek Olšák2019-08-191-4/+7
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* radeonsi: fix an assertion failure: assert(!res->b.is_shared)Marek Olšák2019-08-191-2/+1
| | | | | | | | | | | This only appears to happen on Raven2. Possible way to reproduce: resource_get_handle(WINSYS_HANDLE_TYPE_KMS) --> sets is_shared = true resource_get_handle(WINSYS_HANDLE_TYPE_DMABUF) --> fail Cc: 19.1 19.2 <[email protected]>
* radeonsi: handle the use_ngg_streamout flag in si_update_nggMarek Olšák2019-08-191-5/+18
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* radeonsi: move the tess factor ring size assertion to a place where it mattersMarek Olšák2019-08-192-1/+1
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac/nir: set image=true when loading FMASK for imagesMarek Olšák2019-08-191-1/+1
| | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* etnaviv: rs: add support for 64bpp clearsChristian Gmeiner2019-08-191-7/+5
| | | | | | | | Starting with HALTI2 the RS supports 64bpp clears. Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* etnaviv: update headers from rnndbChristian GMEINER2019-08-1913-115/+204
| | | | | | | | Update to etna_viv commit c51353e. Signed-off-by: Christian GMEINER <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* swrast: Make the fetch funcs table sparse.Eric Anholt2019-08-191-191/+24
| | | | | | | | | This shrinks the table, avoids needing to update the table with NULL entries on every MESA_FORMAT addition, and removes a surprising, non-unit-tested format number ordering dependency. Acked-by: Jose Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* gallium: Remove manual defining of PIPE_FORMAT enum values.Eric Anholt2019-08-191-357/+357
| | | | | | | | | Now that SVGA doesn't have a table that has to be in PIPE_FORMAT order, we can let the enums have whatever values they naturally would without worrying about holes. Acked-by: Jose Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: Drop unsupported formats from the format table.Eric Anholt2019-08-191-170/+0
| | | | | | | | | | | Now that we're using the array initializers, we don't need to manually fill out all these stub entries. Produced with "sed -i '/.*INVALID.*INVALID.*INVALID/d' src/gallium/drivers/svga/svga_format.c" Acked-by: Jose Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: Remove duplication in the format table.Eric Anholt2019-08-191-329/+322
| | | | | | | | | | | | | By using the [ ] = {} array initializer syntax, we no longer need the entries to be listed in PIPE_FORMAT_* value order. This means that people adding new gallium formats don't need to cargo-cult changes to this driver or regress that non-unit-tested requirement. While I'm here, drop the lines for formats that no longer exist (the numbered ones in the table). Acked-by: Jose Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* svga: Factor out the format conversion table entry lookup.Eric Anholt2019-08-191-16/+25
| | | | | | | | | | | Seemed like a sensible cleanup, while I was looking at whether I could make the table sparse. To make the svga table not require fixups on every new gallium format, we may want to change how it's populated. Acked-by: Jose Fonseca <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* nir: Add more source types to nir_tex_instr_src_typeJason Ekstrand2019-08-191-3/+14
| | | | | Reviewed-by: Dave Airlie <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Compute liveness per-blockAlyssa Rosenzweig2019-08-192-70/+169
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than using a regalloc based on live internals, computed hastily with repeated invocations of a forward-analysis pass, we switch to compute liveness information on a per-block basis. Within a given basic block, we compute liveness backwards with a linear-time algorithm; for common shaders, this may help RA terminate quicker. Across blocks, we use a work list (really a work set) and check if we're making progress. This isn't terribly efficient, but it gets the job done. Point is, we get the live_in/live_out for each block. From there, it's simple to rerun the linear-time update algorithm to compute the interference graph. The benefit of this technique is the ability to ignore "gaps" in liveness across intermediate blocks that are never executed. On simple shaders like the loops in glmark, this results in a minor reduction in register pressure. The motivation was a complex shader in Krita that failed register allocation due to an unfortunate interaction between texture pipeline registers and control flow. This shader now compiles successfully. total instructions in shared programs: 3439 -> 3438 (-0.03%) instructions in affected programs: 22 -> 21 (-4.55%) helped: 1 HURT: 0 total bundles in shared programs: 2077 -> 2076 (-0.05%) bundles in affected programs: 12 -> 11 (-8.33%) helped: 1 HURT: 0 total quadwords in shared programs: 3457 -> 3456 (-0.03%) quadwords in affected programs: 20 -> 19 (-5.00%) helped: 1 HURT: 0 total registers in shared programs: 341 -> 338 (-0.88%) registers in affected programs: 9 -> 6 (-33.33%) helped: 3 HURT: 0 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 33.33% max: 33.33% x̄: 33.33% x̃: 33.33% Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Analyze load/store for swizzle propagationAlyssa Rosenzweig2019-08-191-3/+21
| | | | | | | | If there's a nontrivial swizzle fed into an extra (shortened) argument, we bail on copyprop. No glmark changes (since it doesn't use fancy texturing/loads). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Treat cubemaps "stores" as loadsAlyssa Rosenzweig2019-08-195-19/+15
| | | | | | | It's always been ambiguous which they are, but their primary register is their output, not their input; therefore, they are loads. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Clamp cubemap swizzle to XYXXAlyssa Rosenzweig2019-08-191-0/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Clamp st_vary swizzle by number of componentsAlyssa Rosenzweig2019-08-191-1/+2
| | | | | | | Same issue with liveness analysis. If we store out a vec3, we should not reference the .w component. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Use type-appropriate swizzle for texture coordinateAlyssa Rosenzweig2019-08-191-1/+7
| | | | | | | | | | | The texture coordinate for a 2D texture could be a vec2 or a vec3, depending if it's an array texture or not. If it's vec2 (non-array texture), we should not reference the z component; otherwise, liveness analysis will get very confused when z is never written. v2: Fix typo (Ilia). Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Set mask for lowered read-hazard movesAlyssa Rosenzweig2019-08-191-0/+1
| | | | | | | If we need to lower a move for a read from a vec2 texture coordinate, we shouldn't write zw, even incidentally. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Fix texw lowering with complex control flowAlyssa Rosenzweig2019-08-191-1/+1
| | | | | | | | | | | | | | | Fixes shaders with control flow like: out = 0; if (A) { if (B) out = texture(A, ...) } else { out = texture(B, ...) } Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_rewrite_index_dst_single helperAlyssa Rosenzweig2019-08-192-2/+8
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Print predecessors in MIRAlyssa Rosenzweig2019-08-191-0/+5
| | | | | | Just as a sanity check. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Index blocks for printingAlyssa Rosenzweig2019-08-193-2/+10
| | | | | | Better than having pointers flying about. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_foreach_srcAlyssa Rosenzweig2019-08-191-0/+3
| | | | | | This is repeated often enough. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_foreach_instr_in_block_revAlyssa Rosenzweig2019-08-191-0/+2
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_foreach_successor helperAlyssa Rosenzweig2019-08-191-0/+8
| | | | | | Now we should be able to walk the control-flow graph naturally. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_foreach_predecessor utilityAlyssa Rosenzweig2019-08-191-0/+11
| | | | | | It's ugly, but c'est la vie. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Link exit blockAlyssa Rosenzweig2019-08-191-1/+9
| | | | | | | The exit block has been 'dangling' in the successors graph, so let's ensure it's linked in. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Add mir_exit_block helperAlyssa Rosenzweig2019-08-191-0/+13
| | | | | | | The exit block is gauranteed to be empty, signaling the end of the program. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Maintain block predecessor setAlyssa Rosenzweig2019-08-192-3/+20
| | | | | | | | While we already compute the successors array, for backwards data flow analysis, it is useful to walk the control flow graph backwards based on predecessors, so let's compute that information as well. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Use ralloc on ctx/blocksAlyssa Rosenzweig2019-08-191-15/+11
| | | | | | This will allow us to get some level of automatic memory management. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* pan/midgard: Shrink successors[] to 2 lengthAlyssa Rosenzweig2019-08-191-1/+1
| | | | | | A block can't have more. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* nir: Add missing dependency in Android.nir.gen.mkRoman Stratiienko2019-08-191-0/+1
| | | | | | | Fixes incremental build with Android Signed-off-by: Roman Stratiienko <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* ac/nir: Fix store_scratch with a non-full writemaskConnor Abbott2019-08-183-5/+42
| | | | | | | | | | | | By adding one more helper to ac_llvm_build, we can also easily keep vector stores together. Fixes the tests/spec/glsl-1.30/execution/fs-large-local-array-vec4.shader_test piglit test. Fixes: 74470baebbd ("ac/nir: Lower large indirect variables to scratch") Reviewed-by: Marek Olšák <[email protected]
* glsl/standalone: init shader stage in init_gl_program()Vasily Khoruzhick2019-08-171-2/+4
| | | | | | | | | | | Otherwise lima standalone compiler fails when trying to compile fragment shader with: lima_compiler: ../src/compiler/nir/nir.c:55: nir_shader_create: Assertion `si->stage == stage' failed Reviewed-by: Qiang Yu <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]>
* iris: Only request an input mask if the shader needs itJason Ekstrand2019-08-161-1/+3
| | | | | Fixes: aebca3961b "iris: Fix handling of SIMD32 fragment shaders" Reviewed-by: Kenneth Graunke <[email protected]>
* gallium: add back YVU supportXiong, James2019-08-161-5/+5
| | | | | | | | PIPE_FORMAT_YV12 is not handled so switching to PIPE_FORMAT_IYUV and adding back YVU support. Signed-off-by: James Xiong <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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