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* iris: Maintain CPU-side SURFACE_STATE copies for views and surfaces.Kenneth Graunke2019-11-252-55/+136
| | | | | | | | | | | | | | | | | | | | | | When replacing the backing storage for texture buffers, image buffers, and so on, we may need to update the "Surface Base Address" field in any corresponding SURFACE_STATE. This is easier to accomplish if we have a copy on the CPU - we can just compare the current field, update it, and re-upload. This patch adds a CPU-side copy to the new iris_surface_state wrapper struct, and reworks allocation and upload to fill things out on the CPU copy first, then upload that to the GPU when finished. This will be necessary to fix iris_invalidate_resource bugs shortly. Technically, we never replace the backing storage for pipe_surfaces (render targets), so we don't need to make this change there. However, it's nice to have surfaces, sampler views, and image views handled similarly. Plus, if we ever wanted to swap out backing storage for busy textures, we'd need this infrastructure. v2: Properly free memory (caught by Andrii Simiklit)
* iris: Create an "iris_surface_state" wrapper structKenneth Graunke2019-11-252-27/+36
| | | | | | | Today, we only have a state reference to the GPU buffer containing our uploaded SURFACE_STATEs. However, we're going to want a CPU-side copy soon. Making a wrapper struct means we can talk about both together, and also put both in the field called "surface_state".
* iris: Drop 'old_address' parameter from iris_rebind_bufferKenneth Graunke2019-11-253-7/+6
| | | | | | | We can just compare the VERTEX_BUFFER_STATE address field to the current BO's address. When calling rebind, we've already updated the resource to the new buffer, but the state will have the old address.
* iris: Stop mutating the resource in get_rt_read_isl_surf().Kenneth Graunke2019-11-251-19/+14
| | | | | | Mutating fields of global resources is generally not safe, and the only reason we were doing it was to avoid passing an extra parameter to the fill_surface_state helper.
* radeonsi/nir: don't run si_nir_opts again if there is no changeMarek Olšák2019-11-253-12/+16
| | | | | | | 0.3% less overhead Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* radeonsi: initialize the per-context compiler on demandMarek Olšák2019-11-253-2/+6
| | | | | | | This takes a noticable amount of time in piglit and some tests don't need it. Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
* ac: set swizzled bit in cache policy as a hint not to merge loads/storesMarek Olšák2019-11-257-36/+32
| | | | | | LLVM now merges loads and stores for all opcodes, so this must be set. Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: Add a scheduler pass to reduce maximum register pressure.Eric Anholt2019-11-255-0/+1098
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is similar to a scheduler I've written for vc4 and i965, but this time written at the NIR level so that hopefully it's reusable. A notable new feature it has is Goodman/Hsu's heuristic of "once we've started processing the uses of a value, prioritize processing the rest of their uses", which should help avoid the heuristic otherwise making such systematically bad choices around getting texture results consumed. Results for v3d: total instructions in shared programs: 6497588 -> 6518242 (0.32%) total threads in shared programs: 154000 -> 152828 (-0.76%) total uniforms in shared programs: 2119629 -> 2068681 (-2.40%) total spills in shared programs: 4984 -> 472 (-90.53%) total fills in shared programs: 6418 -> 1546 (-75.91%) Acked-by: Alyssa Rosenzweig <[email protected]> (v1) Reviewed-by: Alejandro Piñeiro <[email protected]> (v2) v2: Use the DAG datastructure, fold in the scheduling-for-parallelism patch, include SSA defs in live values so we can switch to bottom-up if we want. v3: Squash in improvements from Alejandro Piñeiro for getting V3D to successfully register allocate on GLES3.1 dEQP. Make sure that discards don't move after store_output. Comment spelling fix.
* etnaviv: implement 64bpp clearJonathan Marek2019-11-2510-19/+41
| | | | | | | | At the same time, update etna_clear_blit_pack_rgba to work with integer formats. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: avoid using RS for 64bpp formatsJonathan Marek2019-11-253-6/+14
| | | | | | | At the same time, this change allows using BLT for 8bpp formats Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* etnaviv: add support for extended pe formatsChristian Gmeiner2019-11-251-2/+8
| | | | | | | | | | | Use the extended format if an such a format was passed. v1 -> v2: - set FORMAT_MASK bit when using ext PE format as suggested by Wladimir J. van der Laan Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* etnaviv: handle 8 byte block in tilingChristian Gmeiner2019-11-251-2/+6
| | | | | | Signed-off-by: Christian Gmeiner <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> Reviewed-by: Jonathan Marek <[email protected]>
* radv: select the depth decompress path based on the aspect maskSamuel Pitoiset2019-11-251-4/+16
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: create decompress pipelines for separate depth/stencil layoutsSamuel Pitoiset2019-11-253-23/+44
| | | | | | | | No functional changes as the driver still uses the depth+stencil pipeline. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rework creation of decompress/resummarize meta pipelinesSamuel Pitoiset2019-11-251-34/+36
| | | | | | | This refactoring will help for creating more decompress pipelines. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set the image view aspect mask before resolvesSamuel Pitoiset2019-11-251-2/+2
| | | | | | | | No functional changes, but it will be used to decompress separate depth/stencil aspects. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set the image view aspect mask during subpass transitionsSamuel Pitoiset2019-11-251-1/+1
| | | | | | | | | No functional changes because the aspect mask is still not used during image transitions but it will be needed for the separate depth/stencil aspects logic. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* aco: enable load/store vectorizerRhys Perry2019-11-251-18/+32
| | | | | | | | | | | | | | | | | | | | | | Totals from affected shaders: SGPRS: 1890373 -> 1900772 (0.55 %) VGPRS: 1210024 -> 1215244 (0.43 %) Spilled SGPRs: 828 -> 828 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 252 -> 252 (0.00 %) dwords per thread Code Size: 81937504 -> 74608304 (-8.94 %) bytes LDS: 746 -> 746 (0.00 %) blocks Max Waves: 230491 -> 230158 (-0.14 %) In NeiR:Automata and GTA V, the code decrease is especially large: -13.79% and -15.32%, respectively. v9: rework the callback function v10: handle load_shared/store_shared in the callback Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Connor Abbott <[email protected]> (v9)
* nir: add load/store vectorizer testsRhys Perry2019-11-252-0/+1763
| | | | | | | | | | | v7: run nir_opt_algebraic v9: rework the callback function v9: update alignment on all loads/stores, even if they're not vectorized v10: add tests for 64-bit offsets v10: add tests for signed offsets Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Connor Abbott <[email protected]> (v9)
* nir: add a load/store vectorization passRhys Perry2019-11-253-0/+1313
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This pass combines intersecting, adjacent and identical loads/stores into potentially larger ones and will be used by ACO to greatly reduce the number of memory operations. v2: handle nir_deref_type_ptr_as_array v3: assume explicitly laid out types for derefs v4: create less deref casts v4: fix shared boolean vectorization v4: fix copy+paste error in resources_different v4: fix extract_subvector() to pass nir_load_store_vectorize_test.ssbo_load_intersecting_32_32_64 v4: rebase v5: subtract from deref/offset instead of scheduling offset calculations v5: various non-functional changes/cleanups v5: require less metadata and preserve more v5: rebase v6: cleanup and improve dependency handling v6: emit less deref casts v6: pass undef to components not set in the write_mask for new stores v7: fix 8-bit extract_vector() with 64-bit input v7: cleanup creation of store write data v7: update align correctly for when the bit size of load/store increases v7: rename extract_vector to extract_component and update comment v8: prevent combining of row-major matrix column acceses v9: rework process_block() to be able to vectorize more v9: rework the callback function v9: update alignment on all loads/stores, even if they're not vectorized v9: remove entry::store_value, since it will not be updated if it's was from a vectorized load v9: fix bug in subtract_deref(), causing artifacts in Dishonored 2 v9: handle nir_intrinsic_scoped_memory_barrier v10: use nir_ssa_scalar v10: handle non-32-bit offsets v10: use signed offsets for comparison v10: improve create_entry_key_from_offset() v10: support load_shared/store_shared v10: remove strip_deref_casts() v10: don't ever pass NULL to memcmp v10: remove recursion in gcd() v10: fix outdated comment v11: use the new nir_extract_bits() v12: remove use of nir_src_as_const_value in resources_different v13: make entry key hash function deterministic v13: simplify mask_sign_extend() v14: add comment in hash_entry_key() about hashing pointers Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Connor Abbott <[email protected]> (v9)
* radv: set alignment for load_ssbo/store_ssbo in meta shadersRhys Perry2019-11-253-0/+26
| | | | | | | Otherwise, nir_intrinsic_align() will assert when called on the intrinsics Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: add nir_num_variable_modes and nir_var_mem_push_constRhys Perry2019-11-252-2/+9
| | | | | | | | | | These will be useful in the upcoming load/store vectorizer. v11: rebase Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* aco: Make unused workgroup id's 0Connor Abbott2019-11-251-3/+3
| | | | | | | It shouldn't matter, but the 1 was leftover from when it was handled together with workgroup_size and num_work_groups. Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Use common argument handlingConnor Abbott2019-11-256-637/+211
| | | | Reviewed-by: Daniel Schürmann <[email protected]>
* radv: Replace supports_spill with explict_scratch_argsConnor Abbott2019-11-256-54/+49
| | | | | | | | | | | The former was always true and hence dead code. We will want to explicitly declare the ring offset register with ACO, but we also want to declare the scratch offset too, and we can't try to disable it since ACO also supports spilling and the determination of whether spilling has to happen occurs well after setting up registers. So replace supports_spill with something that will actually be used for ACO. Reviewed-by: Samuel Pitoiset <[email protected]>
* aco: Make num_workgroups and local_invocation_ids one argument eachConnor Abbott2019-11-252-17/+17
| | | | | | To match the LLVM argument setup code. Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Split vector arguments at the beginningConnor Abbott2019-11-252-2/+20
| | | | | | | | Due to how LLVM works we have to make some of the FS inputs become vectors, and therefore have to split them early so that they don't take up extra register pressure due to how RA currently works. Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Use radv_shader_args in aco_compile_shader()Connor Abbott2019-11-253-13/+13
| | | | Reviewed-by: Daniel Schürmann <[email protected]>
* aco: Constify radv_nir_compiler_options in iselConnor Abbott2019-11-253-4/+4
| | | | | | It's already const for everything else. Reviewed-by: Daniel Schürmann <[email protected]>
* radv: Move argument declaration out of nir_to_llvmConnor Abbott2019-11-256-784/+823
| | | | | | Now it's executed for ACO too. Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir, radv, radeonsi: Switch to using ac_shader_argsConnor Abbott2019-11-2513-1553/+1557
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Acked-by: Marek Olšák <[email protected]>
* ac: Add a shared interface between radv, radeonsi, LLVM and ACOConnor Abbott2019-11-256-0/+273
| | | | | | | | | | | | | | | | | | | ac_shader_args will be similar to ac_shader_abi, except for being free from LLVM-specific concepts and therefore capable of being shared between LLVM and ACO. This will help us accomplish a few different things: - Decouple setting up SGPR and VGPR arguments from translating to LLVM, so that we can reference these arguments in NIR lowering passes, which will let us lower e.g. descriptor sets in NIR. - Stop using radv-specific structures for things like determining the chip generation in ACO. In the end, we should replace ac_shader_abi with this structure + driver-specific lowering passes. Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Rename ac_arg_regfileConnor Abbott2019-11-251-2/+2
| | | | | | | | We'll duplicate this in a header file in the next commit, and then remove the original enum. Just rename it temporarily so that things keep building. Reviewed-by: Samuel Pitoiset <[email protected]>
* drirc: Add glsl_zero_init workaround for GpuTestDanylo Piliaiev2019-11-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | GiMark benchmark from GpuTest has such code in VS: out vec4 lightDir0; out vec4 lightDir1; ... lightDir0.xyz = lp0 - vVertex.xyz; lightDir1.xyz = lp1 - vVertex.xyz; In FS: float distSqr = dot(lightDir0, lightDir0); So due to the usage of uninitialized .w channel in the dot product, distSqr may become undefined which results in many black dots in the test on Iris. In https://www.geeks3d.com/forums/index.php/topic,6242.0.html developer stated that this benchmark most likely won't be updated. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1919 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* meson: only build imgui when neededSamuel Pitoiset2019-11-253-3/+5
| | | | | | | Only required for Intel tools or the Vulkan overlay layer. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* ac/llvm: fix the local invocation index for wave32Samuel Pitoiset2019-11-251-0/+4
| | | | | | | | | | | | Fixes dEQP-VK.compute.builtin_var.local_invocation_index with RADV_PERFTEST=cswave32. My initial fix was to lower it but Rhys suggested the shift-right and it's much better like this. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: disable subgroup shuffle operations on GFX10Samuel Pitoiset2019-11-251-1/+2
| | | | | | | | They are broken like on GFX6-GFX7. It seems better to disable them instead of enabling a broken feature. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* llvmpipe: initial query buffer object support. (v2)Dave Airlie2019-11-252-1/+153
| | | | | | | This fails a couple of piglits due to other bugs in llvmpipe, but it adds support for the feature properly. v2: don't reset pipestats, just recalc, fix CI expectation
* radv: create a fresh fork for each pipeline compileTimothy Arceri2019-11-252-14/+139
| | | | | | | | | | | | | | | | In order to prevent a potential malicious pipeline tainting our secure compile process and interfering with successive pipelines we want to create a fresh fork for each pipeline compile. Benchmarking has shown that simply forking on each pipeline creation doubles the total time it takes to compile a fossilize db collection. So instead here we fork the process at device creation so that we have a slim copy of the device and then fork this otherwise idle and untainted process each time we compile a pipeline. Forking this slim copy of the device results in only a 20% increase in compile time vs a 100% increase. Fixes: cff53da3 ("radv: enable secure compile support")
* radv: add a secure_compile_open_fifo_fds() helperTimothy Arceri2019-11-251-0/+43
| | | | | | | | | | | | | | This will be used to create a communication pipe between the user facing device and a freshly forked (per pipeline compile) slim copy of that device. We can't use pipe() here because the fork will not be a direct fork of the user facing process. Instead we use a previously forked copy of the process that was forked at device creation in order to reduce the resources required for the fork and avoid performance issues. Fixes: cff53da3748d ("radv: enable secure compile support")
* radv: add some infrastructure for fresh forks for each secure compileTimothy Arceri2019-11-251-1/+14
| | | | | | | | | | | | | In the following commits we want to be able to fork an existing lightweight fork created at device creation time. In order for the user facing process to communicate with this new fresh fork we create some members here to hold FIFO file descriptors and a unique id. Here we also add a new fork enum that we use to tell the lightweight process to create a fresh fork. For more information on why we create a fresh fork see the following commits.
* nir: no-op C99 _Pragma() with MSVCBrian Paul2019-11-231-0/+7
| | | | | | | | | | This fixes a build failure on MSVC. BTW, it looks like clang supports _Pragma() but I don't know if it understands the "gcc unroll N" directive. Signed-off-by: Brian Paul <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* disk_cache_get_function_timestamp: check for dladdrMichel Zou2019-11-231-1/+1
| | | | | | instead of dlopen Reviewed-by: Eric Engestrom <[email protected]>
* nir/serialize: support any num_components for remaining instructionsMarek Olšák2019-11-231-4/+13
| | | | | | | | | Only NPOT vectors greater than vec4 use the extra uint32. This is for instructions that share the dest code. load_const and undef already support 1-16 in the header. Reviewed-by: Connor Abbott <[email protected]>
* nir/serialize: use 3 unused bits in intrinsic for packed_const_indicesMarek Olšák2019-11-231-11/+10
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/serialize: don't serialize redundant nir_intrinsic_instr::num_componentsMarek Olšák2019-11-231-6/+16
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/serialize: serialize writemask for vec8 and vec16Marek Olšák2019-11-231-9/+16
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/serialize: serialize swizzles for vec8 and vec16Marek Olšák2019-11-231-8/+43
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/serialize: reuse the writemask field for 2 src X swizzles of SSA ALUMarek Olšák2019-11-231-3/+33
| | | | Reviewed-by: Connor Abbott <[email protected]>
* nir/serialize: remove up to 3 consecutive equal ALU instruction headersMarek Olšák2019-11-231-16/+65
| | | | | | | | | | | vec4 scalarized ALUs typically have 4 equal instruction headers, so remove the last 3. There are no bits left in the ALU header for more flags, so future extensions of NIR will have to use something like instr_type == 15 to describe more complex ALU instructions. Reviewed-by: Connor Abbott <[email protected]>
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