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* iris: Maintain CPU-side SURFACE_STATE copies for views and surfaces.Kenneth Graunke2019-11-252-55/+136
* iris: Create an "iris_surface_state" wrapper structKenneth Graunke2019-11-252-27/+36
* iris: Drop 'old_address' parameter from iris_rebind_bufferKenneth Graunke2019-11-253-7/+6
* iris: Stop mutating the resource in get_rt_read_isl_surf().Kenneth Graunke2019-11-251-19/+14
* radeonsi/nir: don't run si_nir_opts again if there is no changeMarek Olšák2019-11-253-12/+16
* radeonsi: initialize the per-context compiler on demandMarek Olšák2019-11-253-2/+6
* ac: set swizzled bit in cache policy as a hint not to merge loads/storesMarek Olšák2019-11-257-36/+32
* nir: Add a scheduler pass to reduce maximum register pressure.Eric Anholt2019-11-255-0/+1098
* etnaviv: implement 64bpp clearJonathan Marek2019-11-2510-19/+41
* etnaviv: avoid using RS for 64bpp formatsJonathan Marek2019-11-253-6/+14
* etnaviv: add support for extended pe formatsChristian Gmeiner2019-11-251-2/+8
* etnaviv: handle 8 byte block in tilingChristian Gmeiner2019-11-251-2/+6
* radv: select the depth decompress path based on the aspect maskSamuel Pitoiset2019-11-251-4/+16
* radv: create decompress pipelines for separate depth/stencil layoutsSamuel Pitoiset2019-11-253-23/+44
* radv: rework creation of decompress/resummarize meta pipelinesSamuel Pitoiset2019-11-251-34/+36
* radv: set the image view aspect mask before resolvesSamuel Pitoiset2019-11-251-2/+2
* radv: set the image view aspect mask during subpass transitionsSamuel Pitoiset2019-11-251-1/+1
* aco: enable load/store vectorizerRhys Perry2019-11-251-18/+32
* nir: add load/store vectorizer testsRhys Perry2019-11-252-0/+1763
* nir: add a load/store vectorization passRhys Perry2019-11-253-0/+1313
* radv: set alignment for load_ssbo/store_ssbo in meta shadersRhys Perry2019-11-253-0/+26
* nir: add nir_num_variable_modes and nir_var_mem_push_constRhys Perry2019-11-252-2/+9
* aco: Make unused workgroup id's 0Connor Abbott2019-11-251-3/+3
* aco: Use common argument handlingConnor Abbott2019-11-256-637/+211
* radv: Replace supports_spill with explict_scratch_argsConnor Abbott2019-11-256-54/+49
* aco: Make num_workgroups and local_invocation_ids one argument eachConnor Abbott2019-11-252-17/+17
* aco: Split vector arguments at the beginningConnor Abbott2019-11-252-2/+20
* aco: Use radv_shader_args in aco_compile_shader()Connor Abbott2019-11-253-13/+13
* aco: Constify radv_nir_compiler_options in iselConnor Abbott2019-11-253-4/+4
* radv: Move argument declaration out of nir_to_llvmConnor Abbott2019-11-256-784/+823
* ac/nir, radv, radeonsi: Switch to using ac_shader_argsConnor Abbott2019-11-2513-1553/+1557
* ac: Add a shared interface between radv, radeonsi, LLVM and ACOConnor Abbott2019-11-256-0/+273
* radv: Rename ac_arg_regfileConnor Abbott2019-11-251-2/+2
* drirc: Add glsl_zero_init workaround for GpuTestDanylo Piliaiev2019-11-251-0/+7
* meson: only build imgui when neededSamuel Pitoiset2019-11-253-3/+5
* ac/llvm: fix the local invocation index for wave32Samuel Pitoiset2019-11-251-0/+4
* radv: disable subgroup shuffle operations on GFX10Samuel Pitoiset2019-11-251-1/+2
* llvmpipe: initial query buffer object support. (v2)Dave Airlie2019-11-252-1/+153
* radv: create a fresh fork for each pipeline compileTimothy Arceri2019-11-252-14/+139
* radv: add a secure_compile_open_fifo_fds() helperTimothy Arceri2019-11-251-0/+43
* radv: add some infrastructure for fresh forks for each secure compileTimothy Arceri2019-11-251-1/+14
* nir: no-op C99 _Pragma() with MSVCBrian Paul2019-11-231-0/+7
* disk_cache_get_function_timestamp: check for dladdrMichel Zou2019-11-231-1/+1
* nir/serialize: support any num_components for remaining instructionsMarek Olšák2019-11-231-4/+13
* nir/serialize: use 3 unused bits in intrinsic for packed_const_indicesMarek Olšák2019-11-231-11/+10
* nir/serialize: don't serialize redundant nir_intrinsic_instr::num_componentsMarek Olšák2019-11-231-6/+16
* nir/serialize: serialize writemask for vec8 and vec16Marek Olšák2019-11-231-9/+16
* nir/serialize: serialize swizzles for vec8 and vec16Marek Olšák2019-11-231-8/+43
* nir/serialize: reuse the writemask field for 2 src X swizzles of SSA ALUMarek Olšák2019-11-231-3/+33
* nir/serialize: remove up to 3 consecutive equal ALU instruction headersMarek Olšák2019-11-231-16/+65
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