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* llvmpipe: add some whitespace between functions in lp_texture.cBrian Paul2017-08-211-0/+3
* mesa: formatting clean-up in syncobj.cBrian Paul2017-08-211-10/+13
* svga: whitespace clean-up in svga_draw_private.hBrian Paul2017-08-211-29/+27
* gallium/docs: remove old llvmpipe TODOTimothy Arceri2017-08-221-14/+0
* mesa: fix ES only draw if we have vertex positionsTimothy Arceri2017-08-221-2/+2
* glsl: Add prototype for udivmod64()Matt Turner2017-08-211-0/+3
* glsl: Mark functions staticMatt Turner2017-08-2111-36/+36
* i965: Mark functions staticMatt Turner2017-08-213-20/+21
* i965/vec4: Use 'class' src_reg, rather than 'struct' src_regMatt Turner2017-08-211-1/+1
* i965/vec4: Return float from spill_cost_for_type()Matt Turner2017-08-211-1/+1
* anv: Move clamp_int64() inside the IVB checkMatt Turner2017-08-211-1/+1
* glsl: Remove unused private fieldsMatt Turner2017-08-212-5/+2
* mesa: Don't compare unsigned for < 0Matt Turner2017-08-211-1/+1
* egl: Fix inclusion of egl.h+mesa_glinterop.hMatt Turner2017-08-212-2/+2
* radeonsi: don't prefetch VBO descriptors if vertex elements == NULLMarek Olšák2017-08-212-1/+4
* r600g: don't set up and don't call the fetch shader if there are no VS inputsMarek Olšák2017-08-213-1/+7
* i965: Optimize reading the destination typeMatt Turner2017-08-211-1/+3
* i965: Mark brw_hw_type_to_reg_type() as a pure functionMatt Turner2017-08-211-1/+7
* i965: Hide the register type hardware encodingsMatt Turner2017-08-212-31/+31
* i965: Stop using hardware register types directlyMatt Turner2017-08-214-158/+113
* i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.cMatt Turner2017-08-213-39/+45
* i965: Move brw_reg_type_letters() as wellMatt Turner2017-08-216-33/+37
* i965: Switch to using the logical register typesMatt Turner2017-08-212-21/+19
* i965: Add functions to abstract access to register typesMatt Turner2017-08-212-51/+79
* i965: Rename brw_inst's functions that access the register typeMatt Turner2017-08-217-99/+99
* i965: Index brw_hw_reg_type_to_size()'s table by logical typeMatt Turner2017-08-211-39/+19
* i965: Add a brw_hw_type_to_reg_type() functionMatt Turner2017-08-212-0/+29
* i965: Use a common table to translate logical to hardware typesMatt Turner2017-08-211-36/+29
* i965: Extract functions dealing with register types to separate fileMatt Turner2017-08-215-140/+209
* i965: Reverse file/type arguments to register type functionsMatt Turner2017-08-214-13/+15
* i965: Add support for disassembling 64-bit integer immediatesMatt Turner2017-08-212-0/+13
* i965: Use separate enums for register vs immediate typesMatt Turner2017-08-216-129/+144
* i965: Reorder brw_reg_type enum valuesMatt Turner2017-08-215-26/+21
* i965: Validate destination restrictions with vector immediatesMatt Turner2017-08-213-12/+141
* i965: Don't let raw-move check be tricked by immediate vector typesMatt Turner2017-08-211-3/+10
* i965: Only change type of 0.0f to VF if destination stride == 1Matt Turner2017-08-211-1/+2
* i965: Remove CONT/BREAK from instruction compaction testMatt Turner2017-08-211-4/+0
* i965: Test instruction compaction on all supported GensMatt Turner2017-08-211-8/+42
* i965: Silence signed/unsigned comparison warningMatt Turner2017-08-211-1/+1
* i965: Move compaction "prepass" into brw_eu_compact.cMatt Turner2017-08-212-72/+82
* i965: Mark src inst pointer const in compaction codeMatt Turner2017-08-212-12/+13
* vulkan: import 1.0.59 headers and xml.Dave Airlie2017-08-221-8/+45
* Android: Fix LLVM duplicated symbols linking for N and MRob Herring2017-08-213-5/+3
* st/va: add MJPEG for configLeo Liu2017-08-212-1/+5
* st/va: reallocate surface with YUYV streamLeo Liu2017-08-211-0/+17
* st/va: detect MJPEG format from bitstreamLeo Liu2017-08-213-0/+10
* radeon/uvd: add YUYV format support for target bufferLeo Liu2017-08-212-3/+5
* st/va: reallocate surface when interlacedLeo Liu2017-08-211-0/+22
* radeon/video: MJPEG not support stacked video buffersLeo Liu2017-08-211-1/+5
* st/va: make surface allocate functions more usefullyLeo Liu2017-08-212-4/+5
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