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* mesa: rename various buffer bindings to one struct.Dave Airlie2017-10-117-45/+20
| | | | | | | | One binding to bind them all, these are all the same thing. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: align atomic buffer handling code with ubo/ssbo (v1.1)Dave Airlie2017-10-112-44/+92
| | | | | | | | | | | | | | this adds automatic size support to the atomic buffer code, but also realigns the code to act like the ubo/ssbo code. v1.1: add missing blank lines. reindent one block properly. check for NullBufferObj. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Don't try to decode types for non-existent src1.Kenneth Graunke2017-10-101-1/+2
| | | | | | | | | | | | | | KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks has a MOV that hits this validation path. MOVs don't have a src1 file, but calling brw_inst_src1_type() was tripping on src1.file being BRW_IMMEDIATE_VALUE and the hw_type being something invalid for immediates. To work around this, just pretend src1 is src0 if there isn't a src1. Fixes: 2572c2771d0cab0b9bc489d354ede44dfc88547b (i965: Validate "Special Requirements for Handling Double Precision Data Types") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680 Reviewed-by: Alejandro Piñeiro <[email protected]>
* main/format: skip format conversion if src and dst format are equalKarol Herbst2017-10-101-0/+14
| | | | | | | | | | | Fixes 'KHR-GL45.copy_image.functional' on Nouveau and i965. v2: (by Kenneth Graunke) Rewrite patch according to Jason Ekstrand's review feedback. This makes it handle differing strides, which i965 needed. Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: Make _mesa_get_format_bytes handle array formats.Jason Ekstrand2017-10-101-0/+5
| | | | | | This is easier than making callers handle a bunch of special cases. Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Only set the MTYPE flags on GFX9+.Bas Nieuwenhuizen2017-10-111-1/+1
| | | | | | | | Older kernels fail the va_op with this flag set. If the kernel supports GFX9 usefully, it will also support this flag. Fixes: e8d57802fea "radv/gfx9: allocate events from uncached VA space" Reviewed-by: Dave Airlie <[email protected]>
* i965: Disable auxiliary buffers when there are self-dependencies.Kenneth Graunke2017-10-103-25/+37
| | | | | | | | | | | | | | | | | | | Jason and I investigated several OpenGL CTS failures where the tests bind the same texture for rendering and texturing, at the same time. This has defined results as long as the reads happen before writes, or the regions are non-overlapping. Normally, this just works out. However, CCS can cause problems. If the shader is reading one set of pixels, and writing to different pixels that are adjacent, they may end up being covered by the same CCS block. So rendering may be writing a CCS block, while the sampler is trying to read it. Corruption ensues. Disabling CCS is unfortunate, but safe. Fixes several KHR-GL45.texture_barrier.* subtests. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* r600: cleanup llvm ir target selection.Dave Airlie2017-10-111-18/+2
| | | | | | | Only r600 target used now for compute IR. Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* r600: drop tc_L2_dirty bit, this was SI only.Dave Airlie2017-10-113-15/+0
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | This lowers ffma to a * b + c. This seems like it should keep Marek happiest, so we'd never get to the fma instruction emission code. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: lower ffma in nir.Dave Airlie2017-10-111-0/+1
| | | | | | | | | | | | | | | | | So it appears the Vulkan SPIR-V fma opcode can be equivalent to a mad operation, and the fma hw opcode on AMD hw is issued like a double opcode so is slower. Also the radeonsi stack does this. This appears to improve performance on a number of games from Feral, and thanks to Feral for noticing the problem. I'm reposting this one as Marek indicated he thinks this is what we should be doing on AMD hw. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Add R16G16B16A16_SNORM fast clear supportAlex Smith2017-10-111-0/+6
| | | | | | Signed-off-by: Alex Smith <[email protected]> Cc: "17.2" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* broadcom/vc5: Fix handling of 5551 textures using the new gallium format.Eric Anholt2017-10-101-2/+2
| | | | | Like vc4, we have the alpha in the low bit. Fixes a bunch of piglit texwrap failures.
* broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.Eric Anholt2017-10-101-0/+2
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* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-102-4/+45
| | | | Fixes arb_color_buffer_float-clear
* broadcom/vc5: Set up per-MRT clear colors.Eric Anholt2017-10-103-41/+22
| | | | Fixes fbo-mrt-alphatest.
* broadcom/vc5: Fix blendfactor zero handling.Eric Anholt2017-10-101-0/+1
| | | | | I cut the line out to move it up to the top, when putting "0" in the switch made the compiler complain that that wasn't a valid enum.
* broadcom/vc5: Fix Rendering Mode Common Config's color store bitmask.Eric Anholt2017-10-101-1/+1
| | | | | This controls the RTs that get stored by the default resolved store, the same way that the extended resolved store packet has a RT bitmask.
* broadcom/vc5: Add support for f32 render targets.Eric Anholt2017-10-103-13/+38
| | | | | The TLB write code is getting ugly and needs a refactoring (that will hopefully handle TLBU uniform coalescing as well).
* broadcom/vc5: Fix color masks for non-independent blending.Eric Anholt2017-10-101-8/+16
| | | | This gets fbo-mrt-alphatest working except for the second RT's clear color.
* broadcom/vc5: Make the BCL's number of render targets setup match the RCL.Eric Anholt2017-10-101-1/+2
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* braodcom/vc5: Fix tile size setup for MRTs.Eric Anholt2017-10-101-2/+2
| | | | | We need to divide the TLB in two for the 2nd color buffer, and again if the 3rd or 4th are present.
* broadcom/vc5: Start hooking up multiple render targets support.Eric Anholt2017-10-103-17/+48
| | | | We now emit as many TLB color writes as there are color buffers.
* broadcom/vc5: Add support for GL_EXT_provoking_vertex.Eric Anholt2017-10-103-1/+5
| | | | | The bit was missing from the spec, but it's there in the simulator. Fixes the piglit clipflat test.
* braodcom/vc5: Find the actual first TF output for our TF spec.Eric Anholt2017-10-101-1/+6
| | | | This doesn't yet support PSIZ, but gets us at least some of TF working.
* broadcom/vc5: Fix translation of transform feedback's output_register field.Eric Anholt2017-10-101-2/+16
| | | | It's a NIR driver_location, not a slot offset.
* broadcom/vc5: Mark our primitives as needing TF processing.Eric Anholt2017-10-102-4/+18
| | | | | The TF enable state appears to stick around until the next TF enable packet is sent, so we only want to request TF when the shader is using it.
* broadcom/vc5: Fix setup of TF dword output count.Eric Anholt2017-10-102-2/+2
| | | | I missed the "- 1" when reading the spec.
* broadcom/vc5: Fix up a comment from vc4 about the predraw texture setup.Eric Anholt2017-10-101-1/+3
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* broadcom/vc5: Flush the job when mapping a transform feedback buffer.Eric Anholt2017-10-103-0/+32
| | | | | We will want something fancier for reusing a TF output within the same frame, but we at least need this in order for piglit tests to work.
* broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.Eric Anholt2017-10-105-20/+31
| | | | | The interpolation qualifier, if specified, is supposed to take precedence over glShadeModel().
* broadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.Eric Anholt2017-10-103-10/+23
| | | | | | | The HW will halt when you hit a HALT packet, or when you hit the end address. Tell CLIF if there's an end address is so that it can stop correctly. (There was usually a 0 byte after the CL, so it would stop anyway).
* broadcom/vc5: Fix depth and stencil clear values.Eric Anholt2017-10-104-15/+11
| | | | | I had misread the packet description: We always have a 32f depth, and a separate u8 stencil.
* broadcom/vc5: Add missing Z16 format.Eric Anholt2017-10-101-0/+1
| | | | We can render to and sample from it just fine.
* braodcom/vc5: Fix incorrect early Z writes in discard shaders.Eric Anholt2017-10-101-1/+6
| | | | Fixes glsl-fs-discard-02.
* broadcom/compiler: Set up passthrough Z when doing FS discards.Eric Anholt2017-10-103-2/+15
| | | | | | | | In order to keep early-Z from writing early in a discard shader, you need to set the "modifies Z" bit in the shader state (which the new prog_data.discards will indicate). Then, in the shader we do a TLB write to make Z passthrough happen (the QPU result is ignored, so we use a NULL source).
* broadcom/compiler: Don't forget the discard state on TLB Z writes.Eric Anholt2017-10-101-0/+1
| | | | We don't want to write Z for discarded fragments.
* broadcom/compiler: Use defines instead of magic values in TLB write setup.Eric Anholt2017-10-101-6/+33
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* broadcom/vc5: Add proper support for base_vertex and base_instance.Eric Anholt2017-10-103-20/+24
| | | | | | I had base_vertex hacked into the shader state setup like in vc4, but it's not correct for big offsets. Using the proper packet is easier and hopefully means we can re-emit shader state setup less frequently.
* broadcom/xml: Add the vc5 Base Vertex/Base Instance packet.Eric Anholt2017-10-101-0/+6
| | | | This lets us do index_bias and ARB_base_instance.
* broadcom/vc5: Use supertiles and generic tile lists.Eric Anholt2017-10-103-73/+130
| | | | | This massively reduces the size of our RCL setup. It also gets us closer to supporting multicore platforms.
* broadcom/xml: Add a bunch more vc5 tile list management packets.Eric Anholt2017-10-101-0/+60
| | | | We're going to need these for MSAA, and to use the generic per-tile list.
* broadcom/xml: Remove vc5 base packet for tile bin/render mode config.Eric Anholt2017-10-101-10/+0
| | | | | | These existed so I could unpack just the sub-id field to switch on in the old manual CLIF dumper. The new codegen handles sub-id automatically, but only if these stub packets aren't there with an implicit sub-id=0.
* braodcom/xml: Fix a pasteo in vc5 store tile buffer general.Eric Anholt2017-10-101-1/+1
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* broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.Eric Anholt2017-10-1042-2/+9129
| | | | | | | | | | | | | | | | | | | | | | | | | V3D 3.3 is a continuation of the 3D implementation in VC4 (v2.1 and v2.6). V3D 3.3 introduces an MMU (no more CMA allocations) and support for GLES3.1. This driver is not currently conformant, though that will be a target as soon as possible. V3D 3.x parts use a new texture tiling layout common across many Broadcom graphics parts including and the HVS scanout engine. It also massively changes the QPU instructions, introducing a common physical register file (no more A/B split) and half-float instructions, while removing the 4x8 unorm instructions in favor of half-float for talking to fixed function interfaces. Because so much has changed, vc5 is implemented in a separate gallium driver, using only the XML code-generation support from vc4. v2: Fix tile layout for 64bpp textures. Fix texture swizzling for 32-bit returns. Fix up a bit of MRT setup. Sync the simulator to kernel behavior a bit more. Improve uniform debugging code. Rebase on QIR->VIR rename. Move texture state mostly to the CSOs. Improve cache flushing on the simulator. Fix program deletion use-after-frees. Acked-by: Dave Airlie <[email protected]> (uabi plan) Acked-by: Daniel Vetter <[email protected]> (uabi plan)
* broadcom: Add VC5 NIR compiler.Eric Anholt2017-10-1017-0/+7498
| | | | | | | | | | | This is a pretty straightforward fork of VC4's NIR compiler to VC5. The condition codes, registers, and I/O have all changed, making the backend hard to share, though their heritage is still recognizable. v2: Move to src/broadcom/compiler to match intel's layout, rename more "vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts with vc4, use new v3d_debug header, add compiler init/free functions, do texture swizzling in NIR to allow optimization.
* broadcom: Add vc5 CLIF dumpingEric Anholt2017-10-103-0/+312
| | | | | | | | This will be usable with "VC5_DEBUG=cl" on the vc5 driver to stream a CLIF file (the Broadcom equivalent of i965's AUB) to stderr. I haven't tested that this is actually usable with the internal CLIF-consuming tools, but is close enough as a baseline and is useful for visually inspecting the command stream.
* broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.Eric Anholt2017-10-1012-0/+2774
| | | | | | | | | | | | | | | | | Unlike VC4, I've defined an unpacked instruction format with pack/unpack functions to convert to 64-bit encoded instructions. This will let us incrementally put together our instructions and validate them in a more natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to. The pack/unpack unfortuantely are written by hand. While I could define genxml for parts of it, there are many special cases (like operand order of commutative binops choosing which binop is being performed!) and it probably wouldn't come out much cleaner. The disasm unit test ensures that we have the same assembly format as Broadcom's internal tools, other than whitespace changes. v2: Fix automake variable redefinition complaints, add test to .gitignore
* broadcom: Introduce a v3d_debug.h header for vc5 and broadcom Vulkan.Eric Anholt2017-10-103-0/+173
| | | | | | | Unlike vc4, where the compiler and gallium driver live together, for vc5 the compiler will live up in the shared broadcom directory, and need access to the debug flags. Define a set of debug flags and helpers there, so it can be shared between compiler, vc5, and vulkan.
* configure: Add the new "vc5" driver to the list, requiring a simulator.Eric Anholt2017-10-101-1/+1
| | | | | | | | | | | | My intent is to develop the vc5 driver in-tree for some time to build the CL generation and shader compiler code, and keep out-of-tree patches for talking to an actual kernel driver until the kernel driver can be stabilized on the hardware. v2: Define a HAVE_BROADCOM_DRIVERS, like HAVE_INTEL or HAVE_AMD. Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
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