| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | radeon/llvm: Use tablegen pattern to lower bitconvert | Tom Stellard | 2012-05-25 | 4 | -294/+11 |
| * | radeon/llvm: Use a custom inserter to lower FNEG | Tom Stellard | 2012-05-25 | 5 | -22/+15 |
| * | radeon/llvm: Use a custom inserter to lower CLAMP | Tom Stellard | 2012-05-25 | 9 | -84/+41 |
| * | radeon/llvm: Use a custom inserter to lower FABS | Tom Stellard | 2012-05-25 | 10 | -42/+41 |
| * | r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswap | Kai Wasserbäch | 2012-05-25 | 1 | -0/+2 |
| * | draw: fix primitive restart bug by using the index buffer offset | Brian Paul | 2012-05-25 | 1 | -3/+6 |
| * | svga: remove the special zero-stride vertex array code | Brian Paul | 2012-05-25 | 9 | -153/+12 |
| * | gallium/docs: beef up the docs related to color clamping | Brian Paul | 2012-05-25 | 2 | -3/+18 |
| * | util: add GALLIUM_LOG_FILE option for logging output to a file | Brian Paul | 2012-05-25 | 2 | -6/+25 |
| * | i965/msaa: Enable 4x MSAA on Gen7. | Paul Berry | 2012-05-25 | 2 | -9/+9 |
| * | i965/msaa: Implement manual blending operation for Gen7. | Paul Berry | 2012-05-25 | 1 | -23/+67 |
| * | i965/msaa: Modify blorp code to account for Gen7 MSAA layouts. | Paul Berry | 2012-05-25 | 3 | -68/+151 |
| * | i965/msaa: Validate Gen7 surface state constraints. | Paul Berry | 2012-05-25 | 3 | -3/+109 |
| * | i965/msaa: Properly handle sliced layout for Gen7. | Paul Berry | 2012-05-25 | 10 | -58/+162 |
| * | i965/msaa: Add defines for Gen7. | Paul Berry | 2012-05-25 | 1 | -0/+5 |
| * | i965/blorp: Enable blorp blits on Gen7. | Paul Berry | 2012-05-25 | 2 | -2/+4 |
| * | i965/blorp: Implement proper texel fetch messages for Gen7. | Paul Berry | 2012-05-25 | 2 | -2/+31 |
| * | i965/blorp: Use 16 pixel dispatch on Gen7. | Paul Berry | 2012-05-25 | 1 | -1/+9 |
| * | i965/blorp: Allocate space for push constants on Gen7. | Paul Berry | 2012-05-25 | 3 | -30/+28 |
| * | i965/blorp: Set the dynamic state upper bound. | Paul Berry | 2012-05-25 | 1 | -1/+6 |
| * | i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions. | Paul Berry | 2012-05-25 | 3 | -34/+49 |
| * | i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessary | Paul Berry | 2012-05-25 | 4 | -27/+87 |
| * | i965/blorp: Emit sample index in SAMPLE_LD message when necessary | Paul Berry | 2012-05-25 | 2 | -21/+36 |
| * | i965/blorp: Generalize sampling code in preparation for Gen7 | Paul Berry | 2012-05-25 | 1 | -26/+61 |
| * | i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern. | Paul Berry | 2012-05-25 | 1 | -5/+40 |
| * | gallium/targets: pass ldflags parameter to MKLIB | Thomas Gstädtner | 2012-05-25 | 1 | -1/+1 |
| * | Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen" | Vadim Girlin | 2012-05-25 | 2 | -6/+56 |
| * | radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructions | Vadim Girlin | 2012-05-25 | 1 | -0/+20 |
| * | radeon/llvm: prepare to revert the round mode state to default | Vadim Girlin | 2012-05-25 | 1 | -2/+9 |
| * | radeon/llvm: fix sampler index in llvm_emit_tex | Vadim Girlin | 2012-05-25 | 1 | -2/+4 |
| * | radeon/llvm: fix opcode for RECIP_UINT_r600 | Vadim Girlin | 2012-05-25 | 1 | -1/+1 |
| * | radeon/llvm/loader: convert hardcoded gpu name to option | Vadim Girlin | 2012-05-25 | 1 | -2/+3 |
| * | r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operands | Vadim Girlin | 2012-05-25 | 1 | -0/+2 |
| * | i915g: Check for geometry shader earlier in i915_set_constant_buffer. | Vinson Lee | 2012-05-24 | 1 | -4/+4 |
| * | scons: Fix SCons build infrastructure for FreeBSD. | Vinson Lee | 2012-05-24 | 3 | -3/+3 |
| * | radeon/llvm: Lower UDIV using the Selection DAG | Tom Stellard | 2012-05-24 | 8 | -212/+126 |
| * | radeon/llvm: Remove auto-generated AMDIL->ISA conversion code | Tom Stellard | 2012-05-24 | 14 | -280/+28 |
| * | radeon/llvm: Remove AMDIL instructions MULHI, SMUL | Tom Stellard | 2012-05-24 | 3 | -10/+5 |
| * | radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR) | Tom Stellard | 2012-05-24 | 8 | -693/+6 |
| * | radeon/llvm: Remove AMDIL FTOI and ITOF instructions | Tom Stellard | 2012-05-24 | 7 | -316/+7 |
| * | radeon/llvm: Remove AMDIL EXP* instructions | Tom Stellard | 2012-05-24 | 5 | -15/+7 |
| * | radeon/llvm: Remove AMDIL ADD instructions | Tom Stellard | 2012-05-24 | 6 | -179/+4 |
| * | radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT) | Tom Stellard | 2012-05-24 | 8 | -422/+8 |
| * | radeon/llvm: Remove AMDILMachinePeephole pass | Tom Stellard | 2012-05-24 | 4 | -177/+0 |
| * | radeon/llvm: Remove AMDIL CMP instructions and associated lowering code | Tom Stellard | 2012-05-24 | 3 | -661/+22 |
| * | radeon/llvm: Remove AMDIL ROUND_NEAREST instruction | Tom Stellard | 2012-05-24 | 4 | -6/+6 |
| * | radeon/llvm: Remove AMDIL ROUND_POSINF instruction | Tom Stellard | 2012-05-24 | 4 | -6/+10 |
| * | radeon/llvm: Add custom SDNode for FRACT | Tom Stellard | 2012-05-24 | 6 | -6/+10 |
| * | radeon/llvm: Use -1 as true value for SET* integer instructions | Tom Stellard | 2012-05-24 | 3 | -32/+28 |
| * | radeon/llvm: Handle SETGE_INT, SETGE_UINT, and SETGT_UINT opcodes | Tom Stellard | 2012-05-24 | 1 | -0/+6 |
