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* util: android: optimize the rules to generate format_srgb.cChih-Wei Huang2015-04-221-22/+10
| | | | | Signed-off-by: Chih-Wei Huang <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* android: use LOCAL_SHARED_LIBRARIES over TARGET_OUT_HEADERSEmil Velikov2015-04-2215-31/+18
| | | | | | | | | ... to manage the LIBDRM*_CFLAGS. The former is the recommended approach by the Android build system developers while the latter has been depreciated for quite some time. Cc: "10.4 10.5" <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* ilo: remove unused include from Android.mkEmil Velikov2015-04-221-3/+0
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chih-Wei Huang <[email protected]>
* drirc: Add "Second Life" quirk (allow_glsl_extension_directive_midshader).Kenneth Graunke2015-04-211-0/+4
| | | | | | | | | | | | Appears to fix shader compilation. Tested by starting the client, dragging the "quality and speed" slider back and forth, and watching the console output - instead of piles of "shader failed to compile", the CPU seems to be busy compiling shaders. I haven't actually tried to play. Signed-off-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=69226 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71591 Cc: [email protected]
* nir: Fix per-component negation in prog_to_nir's SWZ handling.Kenneth Graunke2015-04-211-7/+18
| | | | | | | | | | I missed the fact that the ARB_fragment_program SWZ instruction allows per-component negation. To fix this, move Abs/Negate handling into both the simple case and the SWZ case's per-component loop. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90000 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: correct indentation of comment, Trivial.Tapani Pälli2015-04-211-1/+1
| | | | Signed-off-by: Tapani Pälli <[email protected]>
* i965/fs: Combine pixel center calculation into one inst.Matt Turner2015-04-213-20/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | The X and Y values come interleaved in g1 (.4-.11 inclusive), so we can calculate them together with a single add(32) instruction on some platforms like Broadwell and newer or in SIMD8 elsewhere. Note that I also moved the PIXEL_X/PIXEL_Y virtual opcodes from before LINTERP to after it. That's because the writes_accumulator_implicitly() function in backend_instruction tests for <= LINTERP for determining whether the instruction indeed writes the accumulator implicitly. The old FS_OPCODE_PIXEL_X/Y emitted ADD instructions, which did, but the new opcodes just emit MOVs, which don't. It doesn't matter, since we don't use these opcodes on Gen4/5 anymore, but in the case that we do... On Broadwell: total instructions in shared programs: 7192355 -> 7186224 (-0.09%) instructions in affected programs: 1190700 -> 1184569 (-0.51%) helped: 6131 On Haswell: total instructions in shared programs: 6155979 -> 6152800 (-0.05%) instructions in affected programs: 652362 -> 649183 (-0.49%) helped: 3179 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Calculate delta_x and delta_y together.Matt Turner2015-04-217-74/+79
| | | | | | | | | | | | | This lets SIMD16 programs on G45 and Gen5 use the PLN instruction. On Ironlake: total instructions in shared programs: 5634757 -> 5518055 (-2.07%) instructions in affected programs: 1745837 -> 1629135 (-6.68%) helped: 11439 HURT: 4 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Emit ADDs for gl_FragCoord, not virtual opcodes.Matt Turner2015-04-215-51/+8
| | | | | | | | | | These were used only on Gen4 and 5. emit_interpolation_setup_gen6() emits ADDs directly. The virtual opcodes weren't providing anything useful. I'm going to repurpose these opcodes, so deleting and readding them makes it simpler to see what's going on. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Manually set source regioning on PLN instructions.Matt Turner2015-04-211-1/+13
| | | | | | | | Like LINE (commit 92346db0), src0 must have a scalar region. Setting src1's region to <8,8,1> lets us pass a properly sized combined delta_xy argument in a few commits without getting a bogus <16,16,1> region. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Add LINTERP's src0 to fs_inst::regs_read().Matt Turner2015-04-211-11/+2
| | | | | | | | | | LINTERP's src0 is PLN's src1, and PLN's src1 reads exec_size / 4 registers. Having that information lets us drop the delta_x/y special case code in split_virtual_grfs(). Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Set compression only if writing two registers.Matt Turner2015-04-211-1/+4
| | | | | | | We don't want to set compression control on a SIMD16 instruction operating on words or smaller. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Allow an execution size of 32.Matt Turner2015-04-212-1/+2
| | | | | | | In a few commits, we'll start emitting an add(32) instruction on some platforms. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make type_sz() return unsigned.Matt Turner2015-04-211-1/+1
| | | | | | Avoids annoying warnings when comparing with sizeof(...). Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Replace guess_execution_size with something simpler.Matt Turner2015-04-214-27/+35
| | | | | | | | | | | | | | | | | | | | | | | guess_execution_size() does two things: 1. Cope with small destination registers. 2. Cope with SIMD8 vs SIMD16 mode. This patch replaces the first with a simple if block in brw_set_dest: if the destination register width is less than 8, you probably want the execution size to match. (I didn't put this in the 3src block because it doesn't seem to matter.) Since only the FS compiler cares about SIMD16 mode, it's easy to just set the default execution size there. This pattern was already been proven in the Gen8+ generator, but we didn't port it back to the existing generator when we combined the two. This is based on a patch from Ken from about a year ago. I've rebased it and and fixed a few bugs. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Ensure delta_x/y are even-aligned registers on Gen6.Matt Turner2015-04-212-3/+3
| | | | | | The BSpec says this applies to Gen6 as well. Reviewed-by: Jason Ekstrand <[email protected]>
* main: remove __FUNCTION__ defined because it is obsoleteMarius Predut2015-04-211-5/+0
| | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Signed-off-by: Marius Predut <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radeon: replace __FUNCTION__ with __func__Marius Predut2015-04-2132-116/+116
| | | | | | | | | Consistently just use C99's __func__ everywhere. No functional changes. Signed-off-by: Marius Predut <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa: add missing break in switch statementTapani Pälli2015-04-211-1/+1
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-By: Martin Peres <[email protected]>
* glsl: add fallthrough comment on switchTapani Pälli2015-04-211-1/+2
| | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-By: Martin Peres <[email protected]>
* mesa: fix UBO queries for active uniformsTapani Pälli2015-04-211-1/+11
| | | | | | | | | | | | | | | Commit 34df5eb introduced regression to GetActiveUniformBlockiv when querying one of the following properties: GL_UNIFORM_BLOCK_ACTIVE_UNIFORMS GL_UNIFORM_BLOCK_ACTIVE_UNIFORM_INDICES Implementation counted all uniforms in ubo directly while query should check first if the uniform in question is _active_. Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90109 Reviewed-By: Martin Peres <[email protected]>
* i965/skl: Fix the qpitch valueNeil Roberts2015-04-202-13/+59
| | | | | | | | | | | | | | | | | | On Skylake the qpitch value is uploaded as part of the surface state so we don't need to add the extra rows that are done for other generations. However for 3D textures it needs to be aligned to the tile height and for depth/stencil textures it needs to be a multiple of 8. Unlike previous generations the qpitch is measured as a multiple of the block size for compressed surfaces. When the horizontal mipmap layout is used for 1D textures then the qpitch is measured in pixels instead of rows. v2: Align the depth/stencil textures to a multiple of 8 v3: Add an assert that ALL_SLICES_AT_EACH_LOD is not used. Ignore the vertical alignment when picking the qpitch for 1D_ARRAY textures. Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965/skl: Don't use ALL_SLICES_AT_EACH_LODNeil Roberts2015-04-201-10/+20
| | | | | | | | | | | | | | | | | | | | | The render surface state command for Skylake doesn't have the surface array spacing bit so it's not possible to select this layout. I think it was only used in order to make it pick a tightly-packed qpitch value that doesn't include space for the mipmaps. However this won't be necessary after the next patch because it will automatically pick a packed qpitch value whenever first_level==last_level. It is better to remove this layout entirely on Gen8+ because although it can effectively be implemented with a small qpitch value when there are no mipmaps it isn't possible to support the case where there are mipmaps because in that case the layout is very different. It could be good to make a similar change for Gen8 if we also change the layouting code to pick the qpitch value in a similar way. v2: Make the commit message and comments more convincing Reviewed-by: Ben Widawsky <[email protected]> Tested-by: Ben Widawsky <[email protected]>
* clover: remove pre llvm 3.5.0 compatibility codeEdB2015-04-201-21/+2
| | | | | Acked-by: Francisco Jerez <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallivm: Fix build against LLVM 3.7 SVN r235265Nick Sarnie2015-04-202-2/+2
| | | | | | | | | LLVM removed JITEmitDebugInfo from TargetOptions since they weren't used v2: Be consistent with the LLVM version check (Aaron Watry) Signed-off-by: Nick Sarnie <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* indices: fix provoking vertex for quads/quadstripsIlia Mirkin2015-04-181-3/+10
| | | | | | | | | | This allows drivers to provide consistent flat shading for quads. Otherwise a driver that only supported tris would have to force last provoking vertex when drawing quads (and would have to say that quads don't follow the provoking vertex convention). Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* primconvert: select pv convention only from flatshade_firstIlia Mirkin2015-04-181-2/+1
| | | | | | | | | This should match to how drivers program hardware. flatshade relates to whether color inputs are interpolated, not the provoking vertex convention. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Rob Clark <[email protected]>
* freedreno/a3xx: enable polymode setting with non-fill modesIlia Mirkin2015-04-181-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: fix integer and 32-bit float border colorsIlia Mirkin2015-04-181-1/+30
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: add support for float R/RG render targetsIlia Mirkin2015-04-181-4/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* mesa/main: add autogenerated format-info.c to gitignoreConnor Abbott2015-04-171-0/+1
| | | | | | | v2: move to right after format-info.h Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* i965: Issue perf_debug messages for unsynchronized maps on !LLC systems.Kenneth Graunke2015-04-171-5/+11
| | | | | | | | | | | | | | | | | We haven't implemented proper unsynchronized map support on !LLC systems (pre-SNB, Atom). MapBufferRange with GL_MAP_UNSYNCHRONIZE_BIT will actually do a synchronized map, probably killing performance. Also warn on BufferSubData, when we should be doing an unsynchronized upload, but instead have to do a synchronous map. v2: Only complain if the buffer is actually busy - we use unsynchronized maps internally for vertex upload and such, but expect those to not be busy. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Tested-by: Ben Widawsky <[email protected]>
* i965: Make shader_time store names/ids instead of referencing shaders.Kenneth Graunke2015-04-172-37/+19
| | | | | | | | | | | | | | | | | | | | | Jason noticed that shader_time was bumping the reference count on the gl_shader_program and gl_program structures, in code called during compilation. Not only were these never unreferenced, but it meant fragment shaders might be referenced twice (SIMD8 and SIMD16)...or only once. We don't actually need the programs. We just need their numeric ID and their language (GLSL/ARB/FF) or KHR_debug label. If there's a label, we have to strdup it since the underlying program could be deleted. To be fair, we're not exactly cleaning that up either, but we at least ralloc it out of the shader_time arrays, so if we ever bother cleaning those up, they'll go away properly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* i965: Delete some unnecessary code in brw_report_shader_time().Kenneth Graunke2015-04-171-6/+1
| | | | | | | | | | | | | It is true that a gl_shader_program with ID 0 will be a fixed-function fragment program; a gl_program with ID 0 but NULL gl_shader_program means that it's a fixed-function vertex shader. But that's not terribly interesting or relevant to what we're doing. We just need to know that ID 0 means "fixed function". Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* i965: Make shader_time use 0 instead of -1 for "no meaningful ID".Kenneth Graunke2015-04-171-8/+6
| | | | | | | | | | | | 0 is not a valid GLSL shader or ARB program ID. For some reason, shader_time used -1 instead...so we had code to detect 0, then override it to -1. We can just delete that. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* adjust a couple of ifdefs to handle NetBSD correctlyTobias Nygren2015-04-173-3/+3
| | | | | Acked-by: Matt Turner <[email protected]> Signed-off-by: Tobias Nygren <[email protected]>
* i965: Render R16G16B16X16 as R16G16B16A16Anuj Phogat2015-04-171-0/+6
| | | | | | | | | | This enables using _mesa_meta_pbo_TexSubImage() to upload data to R16G16B16X16 texture. Earlier it fell back to slower paths. Jenkins run shows no piglit regressions. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Update the comment about platforms supporting blorpAnuj Phogat2015-04-171-2/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* nir: Allow abs/neg in select peephole pass.Matt Turner2015-04-171-1/+3
| | | | | | | | | | | total instructions in shared programs: 4314531 -> 4308949 (-0.13%) instructions in affected programs: 429085 -> 423503 (-1.30%) helped: 1680 HURT: 0 GAINED: 0 LOST: 111 Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: Change SEL and MOV types as needed to propagate source modifiersJason Ekstrand2015-04-171-4/+30
| | | | | | | | | | | | | | | | | | | | SEL and MOV instructions, as long as they don't have source modifiers, are just copying bits around. This commit adds support to copy propagation to switch the type of a SEL or MOV instruction as needed so that it can propagate source modifiers. This is needed because NIR generates integer SEL and MOV instructions whenver it doesn't know what else to generate. shader-db results with NIR: total FS instructions in shared programs: 4360910 -> 4360186 (-0.02%) FS instructions in affected programs: 59094 -> 58370 (-1.23%) helped: 341 HURT: 0 GAINED: 2 LOST: 0 Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Use the source type when looking for UD negations in copy propJason Ekstrand2015-04-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There can be problems with floats and conditional modifiers when copy-propagating a negated UD source. The problem arises when a source modifier is applied to a UD value. In this case, a 33-bit representation is internally used. If you do the following: 1: mov foo:UD 7U 2: mov bar:UD -foo:UD 3: mov out:F bar:UD the out register will have the value (float)(unt32_t)-7 which is some very large floating-point number. However, if we allow copy-propagation of the second mov, we get 1: mov foo:UD 7U 3: mov out:f -bar:UD and, since the negation is computed in 33-bits, we get a value of -7.0f which is clearly not the same. This is a similar problem if the instruction has a conditional modifier where the 33-bit value is used in the comparison and not the 32-bit version. Previously, we checked the source to be copied for the negate and then checked the source being propagated to for the type. This isn't quite what we want because we are really just looking for negated UD sources. A check later in the file ensures that both ends of the propagate have the right type so it works. However, if we relax the restriction that both ends of the propagation have the same type, it ends up causing us to bail early in cases we don't want. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* freedreno/ir3/nir: few little fixesRob Clark2015-04-171-21/+28
| | | | | | | | | isaml needs to scale up coords based on LoD. Also fix bogus bary.f varying # when there are non-bary frag shader inputs. And use sub.s of a positive immediate rather than add.s of negative (since CP is better about figuring out that those can be collapsed into the cat2 instr). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: lower if/elseRob Clark2015-04-176-8/+381
| | | | | | | For now, completely flatten if/else blocks. That will almost certainly change once we have flow control. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: support for large shadersRob Clark2015-04-171-3/+26
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-04-178-42/+354
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/nir: UBO supportRob Clark2015-04-172-0/+52
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move out helperRob Clark2015-04-172-24/+23
| | | | | | We'll also want it in NIR f/e for implementing UBO support. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: sysvals and UBOsRob Clark2015-04-173-24/+56
| | | | | | | | | | Basically just sync up the cmdstream emit parts to match the changes already done on a3xx. Also, fix scheduling for mem instructions. This is needed on a4xx, and I am a bit surprised it isn't needed for a3xx. Signed-off-by: Rob Clark <[email protected]>
* nir/builder: add nir_builder_insert_after_instr()Rob Clark2015-04-171-2/+18
| | | | | | | For lowering if/else, I need a way to insert at the end of the previous block. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: fix TXFRob Clark2015-04-171-1/+7
| | | | | | | | There is a level param stashed away in the .w component of the first src. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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