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* anv/entrypoints: Dump useful data if mako throws an exceptionJason Ekstrand2017-10-251-5/+17
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/opt_intrinsics: Rework progressJason Ekstrand2017-10-251-5/+9
| | | | | | | | | This commit fixes two issues: First, we were returning false regardless of whether or not the function made progress. Second, we were calling nir_metadata_preserve far more often than needed; we only need to call it once per impl. Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/compiler: Call nir_lower_system_values in brw_preprocess_nirJason Ekstrand2017-10-253-4/+2
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/program: Move nir_lower_system_values higher upJason Ekstrand2017-10-251-1/+2
| | | | | | | | We want this to get called before nir_lower_subgroups which is going in brw_preprocess_nir. Now that nir_lower_wpos_ytransform can handle system values, this should be safe to do. Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/lower_wpos_ytransform: Support system value intrinsicsJason Ekstrand2017-10-251-0/+4
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline: Call nir_lower_system_valaues after brw_preprocess_nirJason Ekstrand2017-10-251-1/+2
| | | | | | | | | | We currently have a bug where nir_lower_system_values gets called before nir_lower_var_copies so it will miss any system value uses which come from a copy_var intrinsic. Moving it to after brw_preprocess_nir fixes this problem. Reviewed-by: Lionel Landwerlin <[email protected]> Cc: [email protected]
* anv/pipeline: Drop nir_lower_clip_cull_distance_arraysJason Ekstrand2017-10-251-2/+0
| | | | | | We already handle it in brw_preprocess_nir Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/pipeline: Dump shader immedately after spirv_to_nirJason Ekstrand2017-10-251-0/+15
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/eu: Use EXECUTE_1 for JMPIJason Ekstrand2017-10-252-2/+1
| | | | | | | | | | | | The PRM says "The execution size must be 1." In 73137997e23ff6c11, the execution size was set to 1 when it should have been BRW_EXECUTE_1 (which maps to 0). Later, in dc2d3a7f5c217a7cee9, JMPI was used for line AA on gen6 and earlier and we started manually stomping the exeution size to BRW_EXECUTE_1 in the generator. This commit fixes the original bug and makes brw_JMPI just do the right thing. Reviewed-by: Matt Turner <[email protected]> Fixes: 73137997e23ff6c1145d036315d1a9ad96651281
* i965/fs: Add brw_reg_type_from_bit_size utility methodAlejandro Piñeiro2017-10-251-5/+64
| | | | | | | | | | | | | | | Returns the brw_type for a given ssa.bit_size, and a reference type. So if bit_size is 64, and the reference type is BRW_REGISTER_TYPE_F, it returns BRW_REGISTER_TYPE_DF. The same applies if bit_size is 32 and reference type is BRW_REGISTER_TYPE_HF it returns BRW_REGISTER_TYPE_F v2 (Jason Ekstrand): - Use better unreachable() messages - Add Q types Signed-off-by: Jose Maria Casanova Crespo <[email protected]> Signed-off-by: Alejandro Piñeiro <[email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs/nir: Use the nir_src_bit_size helperJason Ekstrand2017-10-251-9/+3
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* intel/fs: Handle flag read/write aliasing in needs_src_copyJason Ekstrand2017-10-251-1/+3
| | | | | | | | | | | | | | | In order to implement the ballot intrinsic, we do a MOV from flag register to some GRF. If that GRF is used in a SEL, cmod propagation helpfully changes it into a MOV from the flag register with a cmod. This is perfectly valid but when lower_simd_width comes along, it simply splits into two instructions which both have conditional modifiers. This is a problem since we're reading the flag register. This commit makes us check whether or not flags_written() overlaps with the flag values that we are reading via the instruction source and, if we have any interference, will force us to emit a copy of the source. Reviewed-by: Matt Turner <[email protected]> Cc: [email protected]
* clover: Fix compilation after clang r315871Jan Vesely2017-10-252-5/+12
| | | | | | | | | | v2: use a more generic compat function v3: rename and formatting cleanup Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103388 Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> CC: <[email protected]>
* glsl_to_tgsi: remove unused glsl_version variableMarek Olšák2017-10-261-3/+0
| | | | trivial
* radv: Compute ac keys from pipeline key.Bas Nieuwenhuizen2017-10-261-72/+41
| | | | | | | | The beginning of the end for the shader keys. Not entirely sure what I'm going to replace them with for the compiler though, so this is the first step. Reviewed-by: Timothy Arceri <[email protected]>
* radv: Add single pipeline cache key.Bas Nieuwenhuizen2017-10-263-8/+55
| | | | | | | To decouple the key used for info gathering and the cache from whatever we pass to the compiler. Reviewed-by: Timothy Arceri <[email protected]>
* radv: Don't compute as_ls/as_es before hashing.Bas Nieuwenhuizen2017-10-261-14/+12
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* glsl_to_nir: Zero nir_constant in constant_copy for valgrind & nir_serializeJordan Justen2017-10-251-1/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl_to_nir: Zero nir_variable struct for valgrind & nir_serializeJordan Justen2017-10-251-1/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Zero nir_load_const_instr::value for valgrind & nir_serializeJordan Justen2017-10-251-1/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/nir: Zero local index const struct for valgrind & nir_serializeJordan Justen2017-10-251-0/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Zero local_size const struct for valgrind & nir_serializeJordan Justen2017-10-251-0/+1
| | | | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: Add field initializers for glsl_struct_field default constructorJordan Justen2017-10-251-0/+7
| | | | | | | | This helps valgrind when encode_type_to_blob is used. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* compiler/types: Support [de]serializing void typesJason Ekstrand2017-10-251-0/+3
| | | | | Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir/intrinsics: Set the correct num_indices for load_outputJason Ekstrand2017-10-251-1/+1
| | | | | | | Cc: [email protected] Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* glsl: move shader_cache type handling to glsl_typesConnor Abbott2017-10-253-171/+178
| | | | | | | | | Not sure if this is the best place to put it, but we're going to need this for NIR too. Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* vulkan: Update headers and registry to 1.0.64Alex Smith2017-10-261-26/+133
| | | | | Acked-by: Dave Airlie <[email protected]> Signed-off-by: Alex Smith <[email protected]>
* ac/nir: generate correct instruction for atomic min/max on unsigned imagesMatthew Nicholls2017-10-251-2/+4
| | | | | | | | v2: fix silly typo Cc: "17.2 17.3" <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium/util: remove some block alignment assertionsRoland Scheidegger2017-10-251-8/+0
| | | | | | | | | | | | | These assertions were revisited a couple of times in the past, and they still weren't quite right. The problem I was seeing (with some other state tracker) was a copy between two 512x512 s3tc textures, but from mip level 0 to mip level 8. Therefore, the destination has only size 2x2 (not a full block), so the box width/height was only 2, causing the assertion to trigger for src alignment. As far as I can tell, such a copy is completely legal, and because a correct assertion would get ridiculously complicated just get rid of it for good. Reviewed-by: Brian Paul <[email protected]>
* gles2: support for GL_EXT_occlusion_query_booleanHarish Krupo2017-10-253-7/+76
| | | | | | | | | | | | | | | | Following test checking entrypoints passes: dEQP-EGL.functional.get_proc_address.extension.gl_ext_occlusion_query_boolean Piglit test 'ext_occlusion_query_boolean-any-samples' passes with these changes. No changes/regression observed in WebGL occlusion tests or Intel CI. v2: add es2="2.0" for glapi entrypoints, clean up xml dispatch_sanity changes (fix 'make check') Signed-off-by: Harish Krupo <[email protected]> Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: enum checks for GL_EXT_occlusion_query_booleanTapani Pälli2017-10-251-0/+44
| | | | | | | Some of the checks are valid for generic ES 3.2 as well. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radv: print NIR before LLVM IR and disassemblySamuel Pitoiset2017-10-251-7/+10
| | | | | | | | | It's still printed after linking, but it makes more sense to have SPIRV->NIR->LLVM IR->ASM. Fixes: f0a2bbd1a4 (radv: move nir print after linking is done) Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: Fix truncation issue hexifying the cache uuid for the disk cache.Bas Nieuwenhuizen2017-10-251-2/+2
| | | | | | | Going from binary to hex has a 2x blowup. Fixes: 14216252923 'radv: create on-disk shader cache' Reviewed-by: Dave Airlie <[email protected]>
* radv: enable lower to scalar nir passTimothy Arceri2017-10-251-0/+24
| | | | | | This will allow dead components of varyings to be removed. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: add support for explicit component packingTimothy Arceri2017-10-251-16/+52
| | | | | | | | | | | | | | This is needed for RADV to support explicit component packing. This is also required to use the new NIR component splitting / packing passes. V2: - add commponent packing support for interpolate_at* intrinsics - improve store packing support when not all varyings are scalar as spotted by Bas the store source was incorrectly offset. Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* i965: fix unused var warnings in release buildTimothy Arceri2017-10-256-32/+13
| | | | Reviewed-by: Jordan Justen <[email protected]>
* radv: use device name in cache creation like radeonsi.Dave Airlie2017-10-251-2/+3
| | | | | | | | Not sure how useful this is, but it makes it more consistent. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Cc: "17.3" <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: use a define for the transition point between cp and compute shaderDave Airlie2017-10-251-3/+9
| | | | | | | | | | For certain buffer meta ops we can use the CP or a compute shader, we should use a define to rather than hardcoding 4096, allows for easier testing and more consistency. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* i965: Call gen6_upload_push_constants() even when the stage is disabled.Kenneth Graunke2017-10-242-18/+16
| | | | | | | | This properly sets stage_state->push_constant_dirty = true, so that we emit 3DSTATE_CONSTANT_XS to disable the constant buffer for the shader stage. It also sets stage_state->push_const_size = 0. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Drop a bunch of downcasting and upcasting of gl_program pointers.Kenneth Graunke2017-10-241-19/+12
| | | | | | | | We have a gl_program and we want a gl_program. There's no point in converting to brw_program and back again. This probably made more sense in the old days before Tim dropped a layer of subclassing. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move _mesa_shader_write_subroutine_indices down a level.Kenneth Graunke2017-10-242-6/+3
| | | | | | Now we call it in one place instead of making every caller do it. Reviewed-by: Topi Pohjolainen <[email protected]>
* radv: only emit dfsm packets if dfsm is allowed.Dave Airlie2017-10-242-3/+4
| | | | | | | | | radeonsi only emits these when dfsm is enabled, so for now just hinge them on a flag we never set. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* meson: build freedrenoRob Clark2017-10-244-1/+256
| | | | | | | | Mostly copy/pasta from Dylan Baker's conversion of nouveau and i965. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* meson: extract out variable for nir_algebraic.pyRob Clark2017-10-242-1/+3
| | | | | | | | Also needed in freedreno/ir3. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* freedreno/ir3: use a flag instead of setting PYTHONPATHRob Clark2017-10-243-6/+23
| | | | | | | | | | Similar to 848da662224326ccfbe6647bc82f4f89ca22c762, pass an arg to ir3_nir_trig.py to add to python path, rather than using $PYTHONPATH, to prep for meson build support. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* i965: Don't disable CCS for RT dependencies when dispatching compute.Kenneth Graunke2017-10-243-5/+5
| | | | | | | | | | | Compute shaders don't have access to the framebuffer, so there's no point in worrying whether a texture is bound as a render target. This saves a bunch of resolves in GFXBench4 Manhattan 3.1, but doesn't seem to impact performance at all, at least on Apollolake. Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Fix memmem compiler warnings.Eric Anholt2017-10-241-1/+2
| | | | | | | | | | | | | | | | | | | gcc is throwing this warning in my meson build: ../src/intel/compiler/brw_eu_validate.c:50:11: warning argument 1 null where non-null expected [-Wnonnull] return memmem(haystack.str, haystack.len, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ needle.str, needle.len) != NULL; ~~~~~~~~~~~~~~~~~~~~~~~ The first check for CONTAINS has a NULL error_msg.str and 0 len. The glibc implementation will exit without looking at any haystack bytes if haystack.len < needle.len, so this was safe, but silence the warning anyway by guarding against implementation variablility. Fixes: 122ef3799d56 ("i965: Only insert error message if not already present") Reviewed-by: Matt Turner <[email protected]>
* freedreno: per-context fd_pipeRob Clark2017-10-249-12/+20
| | | | | | | | To enable per-context priorities, we need to have per-context pipe's. Unfortunately we still need to keep the global screen pipe, mostly just for screen->get_timestamp(). Signed-off-by: Rob Clark <[email protected]>
* freedreno: rename pipe -> vsc_pipeRob Clark2017-10-246-15/+15
| | | | | | | | To add context priority support we need to have an fd_pipe per context, rather than per-screen. Which conflicts with existing ctx->pipe (which is actually a visibility stream pipe (hw resource). So just rename it. Signed-off-by: Rob Clark <[email protected]>
* freedreno: pass context flags through to fd_context_init()Rob Clark2017-10-246-6/+6
| | | | | | Prep work for later patch. Signed-off-by: Rob Clark <[email protected]>
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