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* nir/glsl: make evaluate_rvalue() return a nir_ssa_def *Connor Abbott2015-11-101-37/+53
* st/mesa: Destroy buffer object's mutex.Jose Fonseca2015-11-101-0/+1
* nir: Store PatchInputsRead and PatchOutputsWritten in nir_shader_info.Kenneth Graunke2015-11-102-0/+7
* vc4: Avoid loading undefined (newly-allocated) FBO contents.Eric Anholt2015-11-091-0/+17
* vc4: Return NULL when we can't make our shadow for a sampler view.Eric Anholt2015-11-091-0/+4
* vc4: Return GL_OUT_OF_MEMORY when buffer allocation fails.Eric Anholt2015-11-092-19/+32
* vc4: Add CL dumping for GL_ARRAY_PRIMITIVE.Eric Anholt2015-11-091-1/+16
* vc4: Fix a compiler warning.Eric Anholt2015-11-091-1/+1
* glsl: Use shared storage variable type for shared variablesJordan Justen2015-11-091-0/+2
* glsl: Add shared variable typeJordan Justen2015-11-092-1/+2
* glsl: Add space to shader_storage in print_visitorJordan Justen2015-11-091-1/+1
* glsl: Align comments on variables typesJordan Justen2015-11-091-7/+7
* glsl: Parse shared keyword for compute shader variablesJordan Justen2015-11-095-1/+17
* glsl: simplify interface block stream qualifier validationTimothy Arceri2015-11-102-23/+14
* st/wgl: add null pointer check for HUD textureBrian Paul2015-11-091-1/+3
* st/wgl: fix double-present on swapbuffers bugBrian Paul2015-11-093-20/+12
* st/wgl: reorder pixel formats to put MSAA formats lastBrian Paul2015-11-091-29/+32
* st/wgl: Don't rely on GDI to bookkeep pixelformat for us.José Fonseca2015-11-092-7/+6
* winsys/radeon: Use CPU page size instead of hardcoding 4096 bytes v3Michel Dänzer2015-11-091-11/+19
* st/omx: add headless supportLeo Liu2015-11-081-10/+35
* st/va: use vl screen drm support from vl_wys_drmLeo Liu2015-11-081-21/+3
* vl: add drm support for vl_screenLeo Liu2015-11-083-1/+85
* st/va: fix build fails with pipe loaderLeo Liu2015-11-081-2/+3
* nvc0: enable compute support on FermiSamuel Pitoiset2015-11-081-2/+2
* nv50/ir: fix emission of s[] args in certain situationsIlia Mirkin2015-11-071-2/+2
* nv50/ir: only take abs value when computing high resultIlia Mirkin2015-11-071-1/+1
* nouveau: avoid queueing too much work onto a single fenceIlia Mirkin2015-11-072-26/+43
* llvmpipe: disable front updates for nowDave Airlie2015-11-081-1/+1
* virgl: wrap ret assignment with braces to do correct thingDave Airlie2015-11-082-2/+2
* nir: Add a nir_deref_tail helperJason Ekstrand2015-11-073-23/+13
* nir/types: Add an is_vector_or_scalar helperJason Ekstrand2015-11-072-0/+7
* i965/fs: Use regs_read/written for post-RA scheduling in calculate_depsJason Ekstrand2015-11-071-11/+4
* nir/validate: Add better validation of load/store typesJason Ekstrand2015-11-071-2/+14
* radeonsi: add register definitions for StoneyMarek Olšák2015-11-071-0/+322
* radeonsi: add workarounds for CP DMA to stay on the fast pathMarek Olšák2015-11-071-5/+88
* radeonsi: unify CP DMA preparation logicMarek Olšák2015-11-071-37/+34
* radeonsi: unify CP DMA code determining various flagsMarek Olšák2015-11-071-28/+23
* radeonsi: only enable write confirmation on the last CP DMA packetMarek Olšák2015-11-071-2/+4
* nv50/ir: allow emission of immediates in imul/imad opsIlia Mirkin2015-11-071-2/+8
* nv50/ir: properly set the type of the constant folding resultIlia Mirkin2015-11-061-4/+4
* nv50/ir: add support for const-folding OP_CVT with F64 source/destIlia Mirkin2015-11-063-0/+45
* nv50/ir: add fp64 opcode emission support for G200 (NVA0)Ilia Mirkin2015-11-061-10/+84
* nv50/ir: Add support for 64bit immediates to checkSwapSrc01Hans de Goede2015-11-061-5/+6
* nvc0/ir: Teach insnCanLoad about double immediatesHans de Goede2015-11-061-6/+19
* nv50/ir: Add support for merge-s to the ConstantFolding passHans de Goede2015-11-061-0/+15
* nv50/ir: disallow 64-bit immediates on nv50 targetsIlia Mirkin2015-11-061-1/+1
* nv50/ir: allow movs with TYPE_F64 destinations to be splitIlia Mirkin2015-11-061-0/+6
* gm107/ir: Add support for double immediatesHans de Goede2015-11-061-1/+4
* nvc0/ir: Add support for double immediatesHans de Goede2015-11-061-0/+8
* i965/nir/fs: Add comment for no-op memory barrier functionsFrancisco Jerez2015-11-061-0/+19
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