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* radv: create on-disk shader cacheTimothy Arceri2017-10-123-0/+34
* radv: remove duplicate debug_flags fieldTimothy Arceri2017-10-129-17/+14
* anv: intel: use anv_image's computed size for importing a BOLionel Landwerlin2017-10-111-11/+15
* anv: bo_cache: allow importing a BO larger than neededLionel Landwerlin2017-10-111-1/+1
* st/glsl_to_tgsi: the second destination doesn't support relative addressingNicolai Hähnle2017-10-111-5/+2
* st/glsl_to_tgsi: fix DFRACEXP with only one destinationNicolai Hähnle2017-10-111-15/+23
* st/glsl_to_tgsi: fix indirect access to 64-bit integerNicolai Hähnle2017-10-111-1/+1
* st/mesa: don't assign prog->ShadowSamplersNicolai Hähnle2017-10-112-5/+0
* st/glsl_to_tgsi: ignore GL_TEXTURE_SRGB_DECODE_EXT for samplers used with tex...Nicolai Hähnle2017-10-118-17/+63
* st/mesa: store state that affects sampler views per contextNicolai Hähnle2017-10-114-41/+44
* swr: simd16 shaders work in progressTim Rowley2017-10-113-2/+21
* gallium: allow 512-bit vectorsTim Rowley2017-10-112-9/+9
* i965: Drop brw_bo_alloc in ARB_indirect_parameters implementation.Kenneth Graunke2017-10-111-1/+1
* i965: Allow mapped VBOs during drawing in non-debug contexts.Kenneth Graunke2017-10-111-0/+3
* meson: fix glx testDylan Baker2017-10-111-0/+1
* nv50,nvc0: fix push hint logic in presence of a start offsetIlia Mirkin2017-10-112-7/+5
* i965: Make brw_update_texture_surface static.Kenneth Graunke2017-10-112-5/+1
* Android: fix build break from r600/radeon splitRob Herring2017-10-103-2/+6
* i965: Fix output register sizes when multiple variables share a slot.Kenneth Graunke2017-10-101-5/+18
* nir: bump loop unroll limit to 96.Dave Airlie2017-10-111-1/+3
* anv: fix assert in wsi image code.Dave Airlie2017-10-111-1/+1
* mesa/st: fix atomic buffer sizing to align with ssbo.Dave Airlie2017-10-111-0/+6
* mesa/bufferobj: consolidate some buffer binding code.Dave Airlie2017-10-111-42/+35
* mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.Dave Airlie2017-10-111-102/+47
* mesa: rename various buffer bindings to one struct.Dave Airlie2017-10-117-45/+20
* mesa: align atomic buffer handling code with ubo/ssbo (v1.1)Dave Airlie2017-10-112-44/+92
* i965: Don't try to decode types for non-existent src1.Kenneth Graunke2017-10-101-1/+2
* main/format: skip format conversion if src and dst format are equalKarol Herbst2017-10-101-0/+14
* mesa: Make _mesa_get_format_bytes handle array formats.Jason Ekstrand2017-10-101-0/+5
* radv: Only set the MTYPE flags on GFX9+.Bas Nieuwenhuizen2017-10-111-1/+1
* i965: Disable auxiliary buffers when there are self-dependencies.Kenneth Graunke2017-10-103-25/+37
* r600: cleanup llvm ir target selection.Dave Airlie2017-10-111-18/+2
* r600: drop tc_L2_dirty bit, this was SI only.Dave Airlie2017-10-113-15/+0
* radeonsi: lower ffma in nir to mad.Dave Airlie2017-10-111-0/+1
* radv: lower ffma in nir.Dave Airlie2017-10-111-0/+1
* radv: Add R16G16B16A16_SNORM fast clear supportAlex Smith2017-10-111-0/+6
* broadcom/vc5: Fix handling of 5551 textures using the new gallium format.Eric Anholt2017-10-101-2/+2
* broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.Eric Anholt2017-10-101-0/+2
* braodcom/vc5: Set up clear color for higher-bpp formats.Eric Anholt2017-10-102-4/+45
* broadcom/vc5: Set up per-MRT clear colors.Eric Anholt2017-10-103-41/+22
* broadcom/vc5: Fix blendfactor zero handling.Eric Anholt2017-10-101-0/+1
* broadcom/vc5: Fix Rendering Mode Common Config's color store bitmask.Eric Anholt2017-10-101-1/+1
* broadcom/vc5: Add support for f32 render targets.Eric Anholt2017-10-103-13/+38
* broadcom/vc5: Fix color masks for non-independent blending.Eric Anholt2017-10-101-8/+16
* broadcom/vc5: Make the BCL's number of render targets setup match the RCL.Eric Anholt2017-10-101-1/+2
* braodcom/vc5: Fix tile size setup for MRTs.Eric Anholt2017-10-101-2/+2
* broadcom/vc5: Start hooking up multiple render targets support.Eric Anholt2017-10-103-17/+48
* broadcom/vc5: Add support for GL_EXT_provoking_vertex.Eric Anholt2017-10-103-1/+5
* braodcom/vc5: Find the actual first TF output for our TF spec.Eric Anholt2017-10-101-1/+6
* broadcom/vc5: Fix translation of transform feedback's output_register field.Eric Anholt2017-10-101-2/+16
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