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* trace: allow GALLIUM_TRACE=stdout/stderrBrian Paul2013-02-011-3/+11
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* radeonsi: port some of get_shader_param changes from r600gMarek Olšák2013-02-011-6/+2
| | | | Reviewed-by: Michel Dänzer <[email protected]>
* mesa: don't expose IBM_rasterpos_clip in a core contextMarek Olšák2013-02-011-1/+1
| | | | | | | | | glRasterPos doesn't exist in the core profile. NOTE: This is a candidate for the stable branches (9.0 and 9.1). Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* r300g: always put MSAA resources in VRAMMarek Olšák2013-02-011-3/+3
| | | | | | | | | This along with the latest drm-fixes branch should help with bad performance of MSAA. Remember: Nx MSAA can't be more than N times slower (where N=2,4,6). Anyway, I recommend at least 512 MB of VRAM for Full HD 6x MSAA. NOTE: This is a candidate for the 9.1 branch.
* r600g: remove broken assert from r600_isa.cVadim Girlin2013-02-011-2/+0
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g: implement shader disassembler v3Vadim Girlin2013-02-013-4/+444
| | | | | | | | | | | | | | R600_DUMP_SHADERS environment var now allows to choose dump method: 0 (default) - no dump 1 - full dump (old dump) 2 - disassemble 3 - both v2: fix output for burst_count > 1 v3: use more human-readable output for kcache data in CF_ALU_xxx clauses, improve output for ALU_EXTENDED, other minor fixes Signed-off-by: Vadim Girlin <[email protected]>
* r600g: use tables with ISA info v3Vadim Girlin2013-02-0110-1789/+2378
| | | | | | | | | v3: added some flags including condition codes for ALU, fixed issue with CF reverse lookup (overlapping ranges of CF_ALU_xxx and other CF instructions) rebased on current master Signed-off-by: Vadim Girlin <[email protected]>
* glapi: Do not use backtrace on MinGW.Vinson Lee2013-01-311-1/+1
| | | | | | | execinfo.h is not available on MinGW. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* r600g: add cs memory usage accounting and limit it v3Jerome Glisse2013-01-317-1/+80
| | | | | | | | | | | | | | | | | | | We are now seing cs that can go over the vram+gtt size to avoid failing flush early cs that goes over 70% (gtt+vram) usage. 70% is use to allow some fragmentation. The idea is to compute a gross estimate of memory requirement of each draw call. After each draw call, memory will be precisely accounted. So the uncertainty is only on the current draw call. In practice this gave very good estimate (+/- 10% of the target memory limit). v2: Remove left over from testing version, remove useless NULL checking. Improve commit message. v3: Add comment to code on memory accounting precision Signed-off-by: Jerome Glisse <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: fix htile buffer leakMarek Olšák2013-01-311-0/+1
| | | | NOTE: This is a candidate for the 9.1 branch.
* mesa: bump version to 9.2 (devel)Andreas Boll2013-01-311-2/+2
| | | | | | | Now that branch 9.1 is created, bump the minor version in master. Reviewed-by: Kenneth Graunke <[email protected]>
* Revert "mesa: Return INVALID_OPERATION when type is known but not allowed"Matt Turner2013-01-301-11/+1
| | | | | | | | | | | | This reverts commit 2906e2034c9d674601960a5b586b6e986e6ef04f. Fixes a regression in the glean depthStencil test. Reverting this does not affect any tests in es3conform, so a more recent patch must have also fixed the failure this one was intended to fix. Reported-by: lu hua <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59494
* mesa: Add TexBufferRange to dispatch_sanity.Kenneth Graunke2013-01-301-1/+1
| | | | | | Christoph implemented this, so we should expect it to be present now. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=60082
* nv50,nvc0: fix/enable texture buffer objectsChristoph Bumiller2013-01-305-33/+42
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* st/mesa: add support for GL_ARB_texture_buffer_rangeChristoph Bumiller2013-01-302-1/+28
| | | | | | | | v2: Update to handle BufferSize being -1 and return a NULL sampler view if the specified range would cause out of bounds access. Reviewed-by: Brian Paul <[email protected]> Acked-by: Ian Romanick <[email protected]>
* gallium: add PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENTChristoph Bumiller2013-01-302-1/+5
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: implement GL_ARB_texture_buffer_rangeChristoph Bumiller2013-01-3011-17/+130
| | | | | | | | | | | | | | | | | | | | | | | v2: Record texObj.BufferSize as -1 in TexBuffer(non-Range) instead of the buffer's current size so we know we always have to use the full size of the buffer object (i.e. even if it changes without the user calling TexBuffer again) for the texture. Clarify invalid offset alignment error message. v3: Use extra GL_CORE-only section in get_hash_params.py for TEXTURE_BUFFER_OFFSET_ALIGNMENT. v4: Remove unnecessary check for profile in _mesa_TexBufferRange. Add check for extension enable in get_tex_level_parameter_buffer. v5: Fix position in gl_API.xml. Add comment about meaning of BufferSize == -1. v6: Add back checks for core profile and add a note about it. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: remove ctx->Driver.Error() hookBrian Paul2013-01-293-12/+0
| | | | | | Not used by any driver anymore. Reviewed-by: Kenneth Graunke <[email protected]>
* glx: Check that swap_buffers_reply is non-NULL before using itStéphane Marchesin2013-01-291-3/+5
| | | | | | | | | Check that the return value from xcb_dri2_swap_buffers_reply is non-NULL before accessing the struct members. Note: This is a candidate for the 9.0 branch. Reviewed-by: Brian Paul <[email protected]>
* mesa: fix comment typo: s/formaat/format/Brian Paul2013-01-291-1/+1
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* llvmpipe: Don't advertise S8_UNORM (with feeble attempt at supporting it).José Fonseca2013-01-292-36/+46
| | | | | | | | | | | | | | S8_UNORM was inadvertedly supported together with Z16_UNORM. I tried to update the code to accomodate stencil-only -- it seemed a simple thing to do -- but "fbo-stencil clear GL_STENCIL_INDEX8" still fails, and it's not worth debugging. Therefore although this change tries to update for S8_UNORM, it also disables it completely. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Fix deferred depth writes for Z16_UNORM.José Fonseca2013-01-291-1/+6
| | | | | | | | | | This special path hadn't been exercised by my earlier testing, and mask values weren't being properly truncated to match the values. This change fixes that. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* draw: fix draw_llvm_variant_key struct padding to avoid recompilesRoland Scheidegger2013-01-293-4/+11
| | | | | | | | | | | | | | The struct padding got broken by c789b981b244333cfc903bcd1e2fefc010500013. This caused serious performance regression because part of the key was uninitialized and hence the shader always recompiled (at least on release builds...). While here also fix key size calculation when the number of samplers and the number of sampler views are different. v2: add comment Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* st/mesa: only enable GL_EXT_framebuffer_multisample if GL_MAX_SAMPLES >= 2Brian Paul2013-01-291-1/+3
| | | | | | | | | We never really have multisampling with one sample per pixel. See also http://bugs.freedesktop.org/show_bug.cgi?id=59873 Note: This is a candidate for the 9.0 branch. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: don't enable GL_EXT_framebuffer_multisample for software driversBrian Paul2013-01-291-1/+0
| | | | | | Note: This is a candidate for the 9.0 branch. Reviewed-by: Jose Fonseca <[email protected]>
* osmesa: use _mesa_generate_mipmap() for mipmap generation, not metaBrian Paul2013-01-291-0/+3
| | | | | | | | See previous commit for more info. Note: This is a candidate for the 9.0 branch. Reviewed-by: José Fonseca <[email protected]>
* xlib: use _mesa_generate_mipmap() for mipmap generation, not metaBrian Paul2013-01-291-0/+3
| | | | | | | | | | | | | | | | | | The swrast fragment program interpreter has trouble computing the right texture LOD because it doesn't have easy access to input derivatives. This causes the GLSL-based meta generate mipmap code to fetch texels from the wrong mipmap level. One possible fix would be to set the GL_TEXTURE_MIN/MAX_LOD parameters to limit sampling from the right level. But let's just use the _mesa_generate_mipmap() fallback since it's a lot faster than using the fragment shader interpreter. Fixes http://bugs.freedesktop.org/show_bug.cgi?id=54240 Note: This is a candidate for the 9.0 branch. Reviewed-by: José Fonseca <[email protected]>
* st/mesa: set ctx->Const.MaxSamples = 0, not 1Brian Paul2013-01-291-0/+4
| | | | | | | | | | The gallium docs for pipe_screen::is_format_supported() says that samples==0 or samples==1 both mean that multisampling is not supported. Return GL_MAX_SAMPLES==0 instead of 1 for consistency with other drivers. Note: This is a candidate for the 9.0 branch. Reviewed-by: Marek Olšák <[email protected]>
* xlib: stop use _mesa_enable_extension(), just set the boolean flagsBrian Paul2013-01-291-5/+4
| | | | Reviewed-by: Ian Romanick <[email protected]>
* xlib: fix incorrect GL_ANGLE_texture_compression_dxt enableBrian Paul2013-01-291-1/+2
| | | | Reviewed-by: Ian Romanick <[email protected]>
* llvmpipe: Support Z16_UNORM as depth-stencil format.José Fonseca2013-01-294-22/+43
| | | | | | | | | | Simply by adjusting the vector element width after/before reading/writing the depth-stencil values. Ran several GL_DEPTH_COMPONENT16 piglit tests without regressions. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* i965: Add chipset limits for Haswell GT1/GT2.Kenneth Graunke2013-01-281-1/+17
| | | | | | | | | | | The maximum number of URB entries come from the 3DSTATE_URB_VS and 3DSTATE_URB_GS state packet documentation; the thread count information comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation. NOTE: This is a candidate for the 9.0 branch. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Eugeni Dodonov <[email protected]>
* intel: Un-hardcode lengths from blitter commands.Kenneth Graunke2013-01-282-7/+7
| | | | | | | | | The packet length may change at some point in the future. Specifying it explicitly (rather than hardcoding it in the command #define) allows us to change it much more easily in the future. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* Remove APIspec.dtdMatt Turner2013-01-281-52/+0
| | | | Left behind by a8ab7e33.
* intel: Use a CPU map of the batch on LLC-sharing architectures.Eric Anholt2013-01-294-9/+24
| | | | | | | | | | | | | | | | Before, we were keeping a CPU-only buffer to accumulate the batchbuffer in, which was an improvement over mapping the batch through the GTT directly (since any readback or other failure to stream through write combining correctly would hurt). However, on LLC-sharing architectures we can do better by mapping the batch directly, which reduces the cache footprint of the application since we no longer have this extra copy of a batchbuffer around. Improves performance of GLBenchmark 2.1 offscreen on IVB by 3.5% +/- 0.4% (n=21). Improves Lightsmark performance by 1.1 +/- 0.1% (n=76). Improves cairo-gl performance by 1.9% +/- 1.4% (n=57). No statistically significant difference in GLB2.1 on SNB (n=37). Improves cairo-gl performance by 2.1% +/- 0.1% (n=278).
* r600g: use uint64_t instead of unsigned long for proper 32bits cpu supportJerome Glisse2013-01-285-16/+16
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: real fix for non 3.8 kernelJerome Glisse2013-01-281-3/+5
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* i965: Fix assignment instead of comparison in asserts.Vinson Lee2013-01-281-2/+2
| | | | | | | | Fixes side effect in assertion defects reported by Coverity. Note: This is a candidate for the 9.1 branch. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* android: use gralloc_drm_get_gem_handle apiTapani Pälli2013-01-283-15/+7
| | | | | | | | Currently a gralloc internal structure is exposed to Mesa, Use a query function instead to maintain ABI compatibility. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* intel: Typo fix: "pitsh" -> "pitch"Paul Berry2013-01-281-1/+1
| | | | Comment change only.
* r600g: fix segfault with old kernel9.1-branchpointJerome Glisse2013-01-285-11/+23
| | | | | | | Old kernel do not have dma support, patch pushed were missing some of the check needed to not use dma. Signed-off-by: Jerome Glisse <[email protected]>
* glx: only advertise GLX_INTEL_swap_event if it's supportedZack Rusin2013-01-241-2/+3
| | | | | | | | | | | Only drivers supporting DRI2 version >=4 support GLX_INTEL_swap_event. So lets mark it as such otherwise applications which use this extension (i.e. everything based on Clutter, e.g. gnome-shell) break horribly on drivers supporting DRI2 versions only up to 3. Note: This is a candidate for the 9.0 branch. Reviewed-by: Brian Paul <[email protected]>
* r600g: improve inputs/interpolation handling with llvm backendVadim Girlin2013-01-284-209/+151
| | | | | | | | | | Get rid of special handling for reserved regs. Use one intrinsic for all kinds of interpolation. v2[Vincent Lejeune]: Rebased against current master Reviewed-by: Tom Stellard <[email protected]> Signed-off-by: Vadim Girlin <[email protected]>
* r600g: Add ar_chan member to struct r600_bytecodeTom Stellard2013-01-283-0/+4
| | | | | | | | r600_bytecode::ar_chan stores the register channel for the value that will be loaded into the AR register. At the moment, this field is only used by the LLVM backend. The default backend always sets ar_chan = 0.
* r600g: More robust checks for MOVA_INT instructionsTom Stellard2013-01-281-8/+35
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* r600g/llvm: Add dummy export for vs outputVincent Lejeune2013-01-281-2/+20
| | | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59588 Reviewed-by: Tom Stellard <[email protected]>
* r600g: Fix building with --enable-r600-llvm-compilerTom Stellard2013-01-281-3/+1
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=59877
* r600g: don't emit WAIT_UNTIL on cayman/TN (v2)Alex Deucher2013-01-281-9/+28
| | | | | | | | | | | | | It shouldn't be needed and older kernels don't support it. v2: Replace with PS partial flush as before. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=59945 Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: add async for staging buffer upload v2Jerome Glisse2013-01-2812-17/+595
| | | | | | v2: Add virtual address to dma src/dst offset for cayman Signed-off-by: Jerome Glisse <[email protected]>
* r600g: add multi ring support with dma as first second ring v4Jerome Glisse2013-01-2814-176/+327
| | | | | | | | | | | | | | | | | | | | | | | | | | | We keep track of ring emission order in a stack, whenever we need to flush we empty the stack in a fifo order. There is few helpers function for bo mapping and other ring activities that will make sure that the ring stack is properly flush and submitted. v2: fix st flush path, and other flush path to properly flush all rings if necessary v3: - improve name of ring helpers - make sure that each time a cs is gona be written it endup at top of the stack to avoid any issue such as : STACK[0] = dma (withbo A,B) STACK[1] = gfx (withbo C,D) Now if code try to emit a dma command relative to bo C or D it will start writting cmd stream into the cs and once it reach the point where it adds relocation it will flush. At that point the cs will have cmd that don't have proper relocation into the relocation buffer and kernel will just refuse to run. v4: - Drop the stack idea as it turn out there is no way to use it or benefit from it. Any time the driver start command on other ring, it always need to flush the previous ring. So make code simpler by not using a stack. Signed-off-by: Jerome Glisse <[email protected]>
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