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* winsys/radeon: allow mapping a user bufferMarek Olšák2015-02-173-2/+8
| | | | | | OpenGL requires this. Reviewed-by: Christian König <[email protected]>
* gallium: add interface and state tracker support for GL_AMD_pinned_memoryMarek Olšák2015-02-1715-5/+39
| | | | | | v2: add alignment restrictions to docs, fix indentation in headers Reviewed-by: Christian König <[email protected]>
* mesa: implement GL_AMD_pinned_memoryMarek Olšák2015-02-174-2/+43
| | | | | | | | | | | | | | It's not possible to query the current buffer binding, because the extension doesn't define GL_..._BUFFER__BINDING_AMD. Drivers should check the target parameter of Drivers.BufferData. If it's equal to GL_EXTERNAL_VIRTUAL_MEMORY_BUFFER_AMD, the memory should be pinned. That's all there is to it. A piglit test is on the piglit mailing list. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Christian König <[email protected]>
* winsys/radeon: add user pointer supportChristian König2015-02-172-0/+113
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: fix AtomicBuffer typo in _mesa_DeleteBuffersMarek Olšák2015-02-171-1/+1
| | | | | Cc: 10.5 10.4 10.3 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeonsi: initialize TC_L2_dirty to false after buffer allocationMarek Olšák2015-02-171-0/+1
| | | | | | I forgot to do this, though "true" should have no effect on correctness. Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: small fix in SPI stateMarek Olšák2015-02-171-2/+4
| | | | | Cc: 10.5 10.4 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: use fences to implement PIPE_QUERY_GPU_FINISHEDMarek Olšák2015-02-171-9/+13
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89014 Reviewed-by: Michel Dänzer <[email protected]>
* r600g,radeonsi: demote TIMESTAMP_DISJOINT query to be a software queryMarek Olšák2015-02-171-14/+13
| | | | | | The query result is always constant. Reviewed-by: Michel Dänzer <[email protected]>
* st/glsl_to_tgsi: fix whitespaceDave Airlie2015-02-171-202/+178
| | | | | | | | | | | | | everytime I open this file in emacs with show trailing whitespace or git add from it my screen flares with red. Just do a general cleanup, makes working on fp64 support not as jarring. I'm not saying this is perfect, its just better than before. Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl/tests: add IMAGE type.Ilia Mirkin2015-02-171-0/+3
| | | | | | | | This fixes a warning when running make check. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* ilo: always set up BLEND_STATE on Gen8Chia-I Wu2015-02-171-7/+1
| | | | There is now an DW0 that seems to be always referenced.
* ilo: fix alpha test on Gen8Chia-I Wu2015-02-171-5/+26
| | | | | Shoudl use GEN8_BLEND_DW0_ALPHA_TEST_ENABLE instead of GEN6_RT_DW1_ALPHA_TEST_ENABLE (and others).
* i965/simd8vs: Fix SIMD8 atomicsBen Widawsky2015-02-161-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The short version: we need to set bits in R0.7 which provide a mask to be used for PS kill samples/pixels. Since the VS has no such concept, we just need to set all 1. The longer version... Execution for SIMD8 atomics is defined as follows: SIMD8: The low 8 bits of the execution mask are ANDed with 8 bits of the Pixel/Sample Mask from the message header. For the typed messages, the Slot Group in the message descriptor selects either the low or high 8 bits. For the untyped messages, the low 8 bits are always selected. The resulting mask is used to determine which slots are read into the destination GRF register (for read), or which slots are written to the surface (for write). If the header is not present, only the low 8 bits of the execution mask are used. The message header for untyped messages is defined in R0.7 "This field contains the 16-bit pixel/sample mask to be used for SIMD16 and SIMD8 messages. All 16 bits are used for SIMD16 messages. For typed SIMD8 messages, Slot Group selects which 8 bits of this field are used. For untyped SIMD8 messages, the low 8 bits of this field are used." Furthermore, "The message header for the untyped messages only needs to be delivered for pixel shader threads, where the execution mask may indicate pixels/samples that are enabled only due to derivative (LOD) calculations, but the corresponding slot on the surface must not be accessed." We're not using a pixel shader here, but AFAICT, this mask is used for all stages. This leaves two options, Remove the header, or make the VS code emit the correct thing for the header. I believe one of the goals of using SIMD8 VS was to get as much code reuse as possible, and so I chose the latter. Since the VS has no such thing as kill instructions, the mask is derived simple as all 1's. v2: Add a comment to the code (stolen from Curro on the mailing list) Change the control flow style (Curro + Jason) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=87258 Cc: Kristian Høgsberg <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa: move assertion after declarations in texstore.cBrian Paul2015-02-161-1/+1
| | | | To fix MSVC build.
* mesa: silence uninitialized var warning in get_tex_rgba_uncompressed()Brian Paul2015-02-161-2/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* meta: Fix saving the results of the current occlusion queryNeil Roberts2015-02-161-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | When restoring the current state in _mesa_meta_end it was previously trying to copy the on-going sample count of the current occlusion query into the new query after restarting it so that the driver will continue adding to the previous value. This wouldn't work for two reasons. Firstly, the query might not be ready yet so the Result member will usually be zero. Secondly the saved query is stored as a pointer to the query object, not a copy of the struct, so it is actually restarting the exact same object. Copying the result value is just copying between identical addresses with no effect. The call to _mesa_BeginQuery will have always reset it back to zero. This patch fixes it by making it actually wait for the query object to be ready before grabbing the previous result. The downside of doing this is that it could introduce a stall but I think this situation is unlikely so it might not matter too much. A better solution might be to introduce a real suspend/resume mechanism to the driver interface. This could be implemented in the i965 driver by saving the depth count multiple times like it does in the i945 driver. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88248 Reviewed-by: Carl Worth <[email protected]> Cc: "10.5" <[email protected]>
* i965/vec4: Override destination register writemask in sampler message send.Francisco Jerez2015-02-161-0/+1
| | | | | | | | | | | | This line was removed by accident in commit 16b911257440afbd77a6eb762e28df62e3c19bc7 causing a regression in the ES3-CTS.gtf.GL3Tests.shadow.shadow_execution_vert Khronos conformance test. It's necessary because the swizzle_result() code below expects all four components of the vector to be valid. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89094 Tested-by: Lu Hua <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Fix a crash in the texture gradient lowering pass with cube samplersIago Toral Quiroga2015-02-161-1/+3
| | | | | | | We need to swizzle the rhs to match the number of components in the writemask, otherwise we'll hit an assertion in ir_assignment. Reviewed-by: Ian Romanick <[email protected]>
* mesa: Fix element count for byte-swaps in texstore, readpix and texgetimageIago Toral Quiroga2015-02-163-15/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some old format conversion code in pack.c implemented byte-swapping like this: GLint comps = _mesa_components_in_format(dstFormat); GLint swapSize = _mesa_sizeof_packed_type(dstType); if (swapSize == 2) _mesa_swap2((GLushort *) dstAddr, n * comps); else if (swapSize == 4) _mesa_swap4((GLuint *) dstAddr, n * comps); where n is the pixel count. But this is incorrect for packed formats, where _mesa_sizeof_packed_type is already returning the size of a pixel instead of the size of a single component, so multiplying this by the number of components in the format results in a larger element count for _mesa_swap than we want. Unfortunately, we followed the same implementation for byte-swapping in the rewrite of the format conversion code for texstore, readpixels and texgetimage. This patch computes the correct element counts for _mesa_swap calls by computing the bytes per pixel in the image and dividing that by the swap size to obtain the number of swaps required per pixel. Then multiplies that by the number of pixels in the image to obtain the swap count that we need to use. Also, when handling byte-swapping in texstore_rgba, we were ignoring the image's depth. This patch fixes this too. Reviewed-by: Jason Ekstrand <[email protected]> Cc: "10.5" <[email protected]>
* mesa: Handle transferOps in texstore_rgbaIago Toral Quiroga2015-02-161-5/+52
| | | | | | | | | In the recent rewrite of the format conversion code we did not handle this. This patch adds the missing support. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89068 Reviewed-by: Jason Ekstrand <[email protected]> Cc: "10.5" <[email protected]>
* i965/fs: Handle U/UW-type immediates in the generator.Matt Turner2015-02-151-0/+6
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* i965/fs: Handle W/UW-type immediates in dump_instructions().Matt Turner2015-02-151-0/+2
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* i965: Let dump_instructions() work before calculate_cfg().Matt Turner2015-02-152-13/+28
| | | | Reviewed-by: Ben Widawsky <[email protected]>
* i965/fs: Call calculate_cfg() before optimize().Matt Turner2015-02-151-2/+4
| | | | | | The CFG is fundamental to the FS IR, not merely a piece of optimization. Reviewed-by: Ben Widawsky <[email protected]>
* i965: Optimize multiplication by -1 into a negated MOV.Matt Turner2015-02-152-0/+14
| | | | | | | instructions in affected programs: 968 -> 942 (-2.69%) helped: 4 Reviewed-by: Ian Romanick <[email protected]>
* i965: Add an is_negative_one() method.Matt Turner2015-02-152-0/+17
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/vec4/vp: Use vec4_visitor::CMP.Matt Turner2015-02-151-2/+1
| | | | | | | | | | | | | | | | | ... instead of emit(BRW_OPCODE_CMP, ...). In commit 6b3a301f I changed vec4_visitor::CMP to set the destination's type to that of src0. In the following commit (2335153f) I removed an apparently now unnecessary work around for Gen8 that did the same thing. But there was a single place that emitted a CMP instruction without using the vec4_visitor::CMP function. Use it there. And change dst_null_d to dst_null_f for good measure, since ARB vp doesn't have integers. Cc: "10.5" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89032 Reviewed-by: Kenneth Graunke <[email protected]>
* ilo: fix some state pointer commands on Gen8Chia-I Wu2015-02-151-0/+20
| | | | | | 3DSTATE_CC_STATE_POINTERS seems to be ignored when bit 0 of DW1 is not set. Follow i965 and set the bit for 3DSTATE_CC_STATE_POINTERS and 3DSTATE_BLEND_STATE_POINTERS. Add gen checks for all state pointer commands.
* nvc0: allow holes in xfb target listsIlia Mirkin2015-02-142-4/+13
| | | | | | | | Tested with a modified xfb-streams test which outputs to streams 0, 2, and 3. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.5" <[email protected]>
* st/mesa: treat resource-less xfb buffers as if they weren't thereIlia Mirkin2015-02-141-1/+1
| | | | | | | | | | | | If a transform feedback buffer's size is 0, st_bufferobj_data doesn't end up creating a buffer for it. There's no point in trying to write to such a buffer, so just pretend as if it's not really there. This fixes arb_gpu_shader5-xfb-streams-without-invocations on nvc0. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "10.4 10.5" <[email protected]>
* nvc0: bail out of 2d blits with non-A8_UNORM alpha formatsIlia Mirkin2015-02-141-2/+5
| | | | | | | | This fixes the teximage-colors uploads with GL_ALPHA format and non-GL_UNSIGNED_BYTE type. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.4 10.5" <[email protected]>
* i965/nir: Don't support gl_FrontFacing as an input variableJason Ekstrand2015-02-141-3/+0
| | | | | Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Make gl_FrontFacing a system_valueJason Ekstrand2015-02-141-2/+8
| | | | | | | | | GLSL IR labels gl_FrontFacing as an input variable and not a system value. This commit makes NIR silently translate gl_FrontFacing to a system value so that it properly gets translated into a load_system_value intrinsic. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/nir: Add support for nir_intrinsic_load_front_faceJason Ekstrand2015-02-141-1/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* nir/lower_phis_to_scalar: Fix some logic in is_phi_scalarizableJason Ekstrand2015-02-141-3/+3
| | | | | Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* clover: Use Legacy PassManager for LLVM trunk (3.7)Shawn Starr2015-02-141-0/+9
| | | | | Reviewed-by: Tom Stellard <[email protected]> Signed-off-by: Shawn Starr <[email protected]>
* ilo: fix JIP/UIP on Gen8Chia-I Wu2015-02-142-9/+25
| | | | UIP is in DW2 and JIP is in DW3 on Gen8. Also, the units are in bytes.
* ilo: do not set GEN6_THREADCTRL_SWITCHChia-I Wu2015-02-141-4/+0
| | | | It is not needed on Gen6+, and it appears to be broken on Gen8.
* ilo: correct ISA UIP/JIP decoding for Gen8Chia-I Wu2015-02-141-18/+39
| | | | JIP is int32_t and UIP is in DW2 on Gen8.
* ilo: prepare for 64-bit immediates decodingChia-I Wu2015-02-141-15/+31
| | | | Replace imm32 by imm64. Add more ways (UD, D, etc) to access the immediate.
* ilo: cleanup ISA DW1 decodingChia-I Wu2015-02-141-34/+55
| | | | Decode the higher and lower 16 bits separately.
* ilo: cleanup ISA DW0 decodingChia-I Wu2015-02-141-10/+16
| | | | | Add disasm_inst_decode_dw0_opcode_gen6() to decode the opcode. Simplify branch_ctrl/acc_wr_ctrl decoding.
* ilo: update some outdated gen checksChia-I Wu2015-02-141-4/+4
| | | | | | Update gen checks for 3DSTATE_POLY_STIPPLE_OFFSET, 3DSTATE_POLY_STIPPLE_PATTERN, 3DSTATE_LINE_STIPPLE, and 3DSTATE_AA_LINE_PARAMETERS.
* ilo: fix rectlist length on Gen8Chia-I Wu2015-02-141-1/+1
| | | | 5 PIPE_CONTROLs, 2 3DSTATE_WM_HZ_OP, and depth buffer setup require 65 DWords.
* ilo: fix 3DSTATE_VF_TOPOLOGYChia-I Wu2015-02-141-2/+1
| | | | The pipe primitive type was wrongly translated twice.
* os,llvmpipe: Set rasterizer thread names on Linux.Jose Fonseca2015-02-132-1/+18
| | | | | | | | | | | To help identify llvmpipe rasterizer threads -- especially when there can be so many. We can eventually generalize this to other OSes, but for that we must restrict the function to be called from the current thread. See also http://stackoverflow.com/a/7989973 Reviewed-by: Roland Scheidegger <[email protected]>
* uti/u_atomic: Don't test p_atomic_add with booleans.Jose Fonseca2015-02-131-6/+19
| | | | | | | | | | | Add another class of tests. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=89112 I failed to spot this in my previous change, because bool was a typedef for char on the system I tested. Reviewed-by: Roland Scheidegger <[email protected]>
* mesa: fix OES_texture_float texture render target behaviorTapani Pälli2015-02-131-0/+12
| | | | | | | | | | | | | | | | | Current implementation allowed usage of unsized type texture GL_FLOAT and GL_HALF_FLOAT as a render target as this was 'expected behavior' by WEBGL_oes_texture_float and is also allowed by the oes-texture-float WebGL test. However this broke some ES3 conformance tests that do not accept such behavior. Patch sets such an fbo incomplete as expected by the ES3 conformance tests. Textures with sized types like RGBA32F will still continue to work as render targets. v2: code style cleanups (Ian Romanick, Matt Turner) Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88905 Reviewed-by: Ian Romanick <[email protected]> Cc: "10.5" <[email protected]>
* vc4: Make SF be a flag on the QIR instructions.Eric Anholt2015-02-128-51/+47
| | | | | | | | | | | | Right now the places that used to emit a mov.sf just put the SF on the previous instruction when it generated the source of the SF value. Even without optimization to push the sf up further (and kill thus potentially kill more MOVs), this gets us: total uniforms in shared programs: 13455 -> 13457 (0.01%) uniforms in affected programs: 3 -> 5 (66.67%) total instructions in shared programs: 40296 -> 40198 (-0.24%) instructions in affected programs: 12595 -> 12497 (-0.78%)
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 02:37:18 +0000