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* radeonsi: remove redundant parameter in r600_init_surfaceMarek Olšák2012-11-281-5/+4
| | | | [ Cherry-picked from r600g commit f5ac60152b10b04d38e77db6b904dd50d1a54d6c ]
* radeonsi: Use explicit stencil mipmap level offsets.Michel Dänzer2012-11-282-7/+6
| | | | | | Extracted from r600g commit 428e37c2da420f7dc14a2ea265f2387270f9bee1. Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: correct texture memory size for Z32F_S8X24Marek Olšák2012-11-281-7/+15
| | | | [ Cherry-picked from r600g commit ea72351a919c594e7f40e901dca42aebb866f8a6 ]
* radeonsi: Depth/stencil fixes.Michel Dänzer2012-11-282-8/+21
| | | | | | Adapted from r600g commit 018e3f75d69490598d61059ece56d379867f3995. Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Flesh out support for depth/stencil exports from the pixel shader.Michel Dänzer2012-11-282-6/+68
| | | | Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Fix sampler views for depth textures.Michel Dänzer2012-11-282-5/+6
| | | | | | | Consistently reference the flushed depth texture in the sampler view, not the original one. Signed-off-by: Michel Dänzer <[email protected]>
* radeonsi: Fix z/stencil texture creation.Jerome Glisse2012-11-281-9/+5
| | | | | | Signed-off-by: Jerome Glisse <[email protected]> [ Cherry-picked from r600g commit b4f0ab0b22625ac1bb3cf16342039557c086ebae ]
* scons: Build ws_xlib on Mac OS X.Vinson Lee2012-11-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes this SCons build error on Mac OS X if X11 is found. NameError: name 'ws_xlib' is not defined: File "SConstruct", line 144: duplicate = 0 # http://www.scons.org/doc/0.97/HTML/scons-user/x2261.html File "scons-2.2.0/SCons/Script/SConscript.py", line 614: return method(*args, **kw) File "scons-2.2.0/SCons/Script/SConscript.py", line 551: return _SConscript(self.fs, *files, **subst_kw) File "scons-2.2.0/SCons/Script/SConscript.py", line 260: exec _file_ in call_stack[-1].globals File "src/SConscript", line 34: SConscript('gallium/SConscript') File "scons-2.2.0/SCons/Script/SConscript.py", line 614: return method(*args, **kw) File "scons-2.2.0/SCons/Script/SConscript.py", line 551: return _SConscript(self.fs, *files, **subst_kw) File "scons-2.2.0/SCons/Script/SConscript.py", line 260: exec _file_ in call_stack[-1].globals File "src/gallium/SConscript", line 135: 'targets/libgl-xlib/SConscript', File "scons-2.2.0/SCons/Script/SConscript.py", line 614: return method(*args, **kw) File "scons-2.2.0/SCons/Script/SConscript.py", line 551: return _SConscript(self.fs, *files, **subst_kw) File "scons-2.2.0/SCons/Script/SConscript.py", line 260: exec _file_ in call_stack[-1].globals File "src/gallium/targets/graw-xlib/SConscript", line 9: ws_xlib, Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* vbo: move another line of code after declarationsBrian Paul2012-11-271-1/+1
| | | | Signed-off-by: Brian Paul <[email protected]>
* vbo: move code after declarations to fix MSVC errorsBrian Paul2012-11-271-7/+7
| | | | Reviewed-by: Ian Romanick <[email protected]>
* vbo: minor whitespace fixBrian Paul2012-11-271-1/+1
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* mesa: remove '(void) k' linesBrian Paul2012-11-271-4/+0
| | | | Serves no purpose as the k parameter is used later in the code.
* mesa/vbo: Check for invalid types in various packed vertex functions.Kenneth Graunke2012-11-271-0/+43
| | | | | | | | | | | | | | According to the ARB_vertex_type_2_10_10_10_rev specification: "The error INVALID_ENUM is generated by VertexP*, NormalP*, TexCoordP*, MultiTexCoordP*, ColorP*, or SecondaryColorP if <type> is not UNSIGNED_INT_2_10_10_10_REV or INT_2_10_10_10_REV." Fixes 7 subcases of oglconform's packed-vertex test. v2: Add "gl" prefix to error messages (pointed out by Brian). Also rebase atop the ctx plumbing. Reviewed-by: Brian Paul <[email protected]>
* mesa/vbo: Support the ES 3.0 signed normalized scaling rules.Kenneth Graunke2012-11-271-2/+38
| | | | | | | | | | | | | | Traditionally, OpenGL has had two separate equations for converting from signed normalized fixed-point data to floating point data. One was used primarily for vertex data, while the other was primarily for texturing and framebuffer data. However, ES 3.0 and GL 4.2 change this, declaring there's only one equation to be used in all cases. Unfortunately, it's the other one. v2: Correctly convert 0b10 to -1.0, as pointed out by Chris Forbes. Reviewed-by: Chris Forbes <[email protected]>
* mesa/vbo: Plumb ctx through to the conv_i(10|2)_to_norm_float functions.Kenneth Graunke2012-11-271-59/+59
| | | | | | | | | The rules for converting these values actually depend on the current context API and version. The next patch will implement those changes. v2: Mark ctx as const, as suggested by Brian. Reviewed-by: Chris Forbes <[email protected]>
* mesa: Set transform feedback's default buffer mode to INTERLEAVED_ATTRIBSMatt Turner2012-11-271-0/+2
| | | | | | | Fixes part of es3conform's transform_feedback_init_defaults test. NOTE: This is a candidate for the stable branch. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Return 0 for XFB_VARYING_MAX_LENGTH if no varyingsMatt Turner2012-11-271-21/+15
| | | | | | | | | v2: Perform this count the same way as elsewhere in this file, per Brian Paul's review. Fixes part of es3conform's transform_feedback_init_defaults test. NOTE: This is a candidate for the stable branches. Reviewed-by: Brian Paul <[email protected]>
* gallium/tests/trivial: updates for transfer functions changesAndreas Boll2012-11-271-10/+4
| | | | | | | | | Fixes build error with configure option --enable-gallium-tests introduced in 369e46888904c6d379b8b477d9242cff1608e30e Compile tested only. Reviewed-by: Marek Olšák <[email protected]>
* gallium/tests/trivial: updates for CSO interface changesAndreas Boll2012-11-271-2/+2
| | | | | | | | Fixes build error with configure option --enable-gallium-tests introduced in ea6f035ae90895bd4ee3247408eb179dfdf96d22 Cc: Brian Paul <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/tests/trivial: updates for util_draw_vertex_buffer changesAndreas Boll2012-11-272-2/+2
| | | | | | | Fixes build error with configure option --enable-gallium-tests introduced in e73bf3b805de78299f1a652668ba4e6eab9bac94 Reviewed-by: Marek Olšák <[email protected]>
* util: Modified u_rect to default to memcpy.James Benton2012-11-271-8/+1
| | | | | | | | Previously this function would assert if the format didn't fit an expected 4 channel format size. Now will work with any format type with any amount of channels. Signed-off-by: José Fonseca <[email protected]>
* util/format: Fix bug in float to non-float conversion in u_format_pack.py.James Benton2012-11-271-1/+1
| | | | Signed-off-by: José Fonseca <[email protected]>
* gallivm: Fix bug in lp_build_one which would incorrectly return a vector for ↵James Benton2012-11-271-1/+1
| | | | | | length 1. Signed-off-by: José Fonseca <[email protected]>
* glsl: Support unsigned integer constants in layout qualifiers.Kenneth Graunke2012-11-261-1/+6
| | | | | | | Fixes es3conform's explicit_attrib_location_integer_constants. Reviewed-by: Eric Anholt <[email protected]> Reviewed-and-tested-by: Matt Turner <[email protected]>
* i965/fs: Move struct brw_compile (p) entirely inside fs_generator.Kenneth Graunke2012-11-266-6/+4
| | | | | | | | | | | | | | | | The brw_compile structure contains the brw_instruction store and the brw_eu_emit.c state tracking fields. These are only useful for the final assembly generation pass; the earlier compilation stages doesn't need them. This also means that the code generator for future hardware won't have access to the brw_compile structure, which is extremely desirable because it prevents accidental generation of Gen4-7 code. v2: rzalloc p, as suggested by Eric. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Split final assembly code generation out of fs_visitor.Kenneth Graunke2012-11-263-78/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Compiling shaders requires several main steps: 1. Generating FS IR from either GLSL IR or Mesa IR 2. Optimizing the IR 3. Register allocation 4. Generating assembly code This patch splits out step 4 into a separate class named "fs_generator." There are several reasons for doing so: 1. Future hardware has a different instruction encoding. Splitting this out will allow us to replace fs_generator (which relies heavily on the brw_eu_emit.c code and struct brw_instruction) with a new code generator that writes the new format. 2. It reduces the size of the fs_visitor monolith. (Arguably, a lot more should be split out, but that's left for "future work.") 3. Separate namespaces allow us to make helper functions for generating instructions in both classes: ADD() can exist in fs_visitor and create IR, while ADD() in fs_generator() can create brw_instructions. (Patches for this upcoming.) Furthermore, this patch changes the order of operations slightly. Rather than doing steps 1-4 for SIMD8, then 1-4 for SIMD16, we now: - Do steps 1-3 for SIMD8, then repeat 1-3 for SIMD16 - Generate final assembly code for both modes together This is because the frontend work can be done independently, but final assembly generation needs to pack both into a single program store to feed the GPU. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Abort on unsupported opcodes rather than failing.Kenneth Graunke2012-11-261-1/+1
| | | | | | | | | | | | | Final code generation should never fail. This is a bug, and there should be no user-triggerable cases where this could occur. Also, we're not going to have a fail() method in a moment. v2: Just abort() rather than assert, to cover the NDEBUG case (suggested by Eric). Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Make it possible to create a cfg_t without a backend_visitor.Kenneth Graunke2012-11-262-3/+18
| | | | | | | | | | All we really need is a memory context and the instruction list; passing a backend_visitor is just convenient at times. This will be necessary two patches from now. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Move uses of brw_compile from do_wm_prog to brw_wm_fs_emit.Kenneth Graunke2012-11-263-14/+20
| | | | | | | | | | | | The brw_compile structure is closely tied to the Gen4-7 hardware encoding. However, do_wm_prog is very generic: it just calls out to get a compiled program and then uploads it. This isn't ultimately where we want it, but it's a step in the right direction: it's now closer to the code generator. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Pass the brw_context pointer into fs_visitor explicitly.Kenneth Graunke2012-11-263-5/+7
| | | | | | | | We used to steal it out of the brw_compile struct...but fs_visitor isn't going to have one of those in the future. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Move brw_wm_compile::fp to fs_visitor.Kenneth Graunke2012-11-268-17/+19
| | | | | | | | Also change it from a brw_fragment_program to a gl_fragment_program, since that seems to be what everything wants anyway. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Remove struct brw_shader * parameter to fs_visitor constructor.Kenneth Graunke2012-11-263-5/+8
| | | | | | | | | | We can easily recover it from prog, and this makes it clear that we aren't passing additional information in. v2: Use an if-statement rather than the ?: operator (suggested by Eric). Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Move brw_wm_compile::dispatch_width into fs_visitor.Kenneth Graunke2012-11-269-66/+64
| | | | | | | | | | | | | | Also, rather than having brw_wm_fs_emit poke at it directly, make it a parameter to the fs_visitor constructor. All other changes generated by search and replace (with occasional whitespace fixup). v2: Make dispatch_width const (as suggested by Paul); fix doxygen mistake (pointed out by Eric); update for rebase. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Move brw_wm_lookup_iz() to fs_visitor::setup_payload_gen4().Kenneth Graunke2012-11-265-85/+82
| | | | | | | This necessitates compiling brw_wm_iz.c as C++. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Move brw_wm_payload_setup() to fs_visitor::setup_payload_gen6()Kenneth Graunke2012-11-264-68/+63
| | | | | | | | Now that we only have the one backend, there's no real point in keeping this separate. Moving it should allow some future simplifications. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Remove brw_wm_compile::computes_depth field.Kenneth Graunke2012-11-264-6/+1
| | | | | | | | | | Everybody determines this by checking if fp's OutputsWritten field contains the FRAG_RESULT_DEPTH bit. Rather than having payload setup check this and set the computes_depth flag, we can just do the check in the only place that actually used it: emit_fb_writes(). Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* gallivm: use the new mip per quad handling in texture fetch pathRoland Scheidegger2012-11-273-193/+212
| | | | | | | | | | No longer have to split fetching into quads dynamically if mip levels are not the same for all quads (aos sampling still always splits due to performance reasons). Instead handle multiple mip levels further down, minification etc. takes this into account. Reviewed-by: José Fonseca <[email protected]>
* gallivm,llvmpipe: handle TXF (texelFetch) instruction, including offsetsRoland Scheidegger2012-11-2713-71/+618
| | | | | | | | | | | | | This also adds some code to handle per-quad lods for more than 4-wide fetches, because otherwise I'd have to integrate the texelFetch function into the splitting stuff... (but it is not used yet outside texelFetch). passes piglit fs-texelFetch-2D, fails fs-texelFetchOffset-2D due to I believe a test error (results are undefined for out-of-bounds fetches, we return whatever is at offset 0, whereas the test expects [0,0,0,1]). Texel offsets are only handled by texelFetch for now, though the interface can handle it for everything. Reviewed-by: José Fonseca <[email protected]>
* i965: Enable ARB_vertex_type_2_10_10_10_rev on Gen4+.Chris Forbes2012-11-261-0/+1
| | | | | | | | v2 (Kayden): Move the enable into an existing intel->gen >= 4 block (as suggested by Ian). Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: emit w/a for packed attribute formats in VSChris Forbes2012-11-263-13/+126
| | | | | | | | | | | | | | | | Implements BGRA swizzle, sign recovery, and normalization as required by ARB_vertex_type_10_10_10_2_rev. V2: Ported to the new VS backend, since that's all that's left; fixed normalization. V3: Moved fixups out of the GLSL-only path, so it works for FF/VP too. V4 (Kayden): Rework ES3 normalization, don't heap allocate registers; tidy comments. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: set attribute w/a bits for packed formatsChris Forbes2012-11-261-4/+26
| | | | | | | | Flag the need for various workarounds to be applied by the vertex shader. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Generalize GL_FIXED VS w/a supportChris Forbes2012-11-263-14/+26
| | | | | | | | | | | Next few patches build on this to add other workarounds for packed formats. V2: rename BRW_ATTRIB_WA_COMPONENTS to BRW_ATTRIB_WA_COMPONENT_MASK; V3 (Kayden): remove separate bit for ES3 signed normalization Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: support 2_10_10_10 formats in get_surface_type.Chris Forbes2012-11-261-1/+19
| | | | | | | | | Always use R10G10B10A2_UINT; Most of the other formats we'd like don't actually work on the hardware. Will emit w/a for scaling, sign recovery and BGRA swizzle in the VS. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: implement get_size for 2_10_10_10 formatsChris Forbes2012-11-261-0/+5
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/vs: add support for emitting SHL, SHR, ASRChris Forbes2012-11-262-4/+10
| | | | | Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Use correct glGetTransformFeedbackVarying name in error msgMatt Turner2012-11-261-2/+2
| | | | Reviewed-by: Brian Paul <[email protected]>
* i965: Fix hangs with FP KIL instructions pre-gen6.Eric Anholt2012-11-251-0/+2
| | | | | | | | | We can't support IF statements in 16-wide on these. To get back to 16-wide for these shaders, we need to support predicate on discard instructions in the backend IR, which is something we've sort of got on the list to do anyway. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55828 Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4: Fix memory leak each time compile_gs_prog() is called.Eric Anholt2012-11-251-1/+1
| | | | | | | | | Commit 774fb90db3e83d5e7326b7a72e05ce805c306b24 introduced a ralloc context to each user of struct brw_compile, but for this one a NULL context was used, causing the later ralloc_free(mem_ctx) to not do anything. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=55175 NOTE: This is a candidate for the stable branches.
* i965/gen4: Fix LOD bias texturing since my fixed reg classes change.Eric Anholt2012-11-251-10/+18
| | | | | | | | | | We have a special case where non-shadow comparison with LOD requires using a SIMD16 vec4 in an 8-wide shader, which appears in the register allocator as a size 8 vgrf. Fixes assertions in various piglit tests and webgl conformance. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56521
* r600g: fix broken streamout if streamout_begin caused a context flushMarek Olšák2012-11-231-2/+6
| | | | | | | This fixes graphics corruption in the case where the DISCARD_RANGE flag is used to map a buffer. NOTE: This is a candidate for the stable branches.
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