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* i965/cfg: Embed exec_node in bblock_link.Matt Turner2014-05-155-23/+25
| | | | | | | In order to remove bblock_link's inheritance of exec_node. Also makes linked list walk code much nicer. Acked-by: Eric Anholt <[email protected]>
* i965/cfg: Make brw_cfg.h closer to C-includable.Matt Turner2014-05-151-13/+23
| | | | | | Only bblock_link's inheritance left. Acked-by: Eric Anholt <[email protected]>
* i965/cfg: Protect brw_cfg.h from multiple inclusion.Matt Turner2014-05-151-0/+6
| | | | Acked-by: Eric Anholt <[email protected]>
* glsl: Add C-callable fprint_ir function.Matt Turner2014-05-152-0/+10
| | | | | Acked-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fb: Use meta path for stencil up/downsamplingTopi Pohjolainen2014-05-151-1/+8
| | | | | | Cc: "10.2" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/meta: Stencil blit for miptree updownsamplingTopi Pohjolainen2014-05-152-0/+38
| | | | | | Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fb: Use meta path for stencil blitsTopi Pohjolainen2014-05-151-0/+9
| | | | | | | | | This is effective only on gen8 for now as previous generations still go through blorp. Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/meta: Stencil blitsTopi Pohjolainen2014-05-153-0/+497
| | | | | | | | | | | | | v2: Create the intel renderbuffer with level hardcoded to zero instead of overriding it in the surface state configuration. Also moved the dimension adjustments for tiling, mip level, msaa into the render buffer creation. Finally prepares for another blit path needed for miptree updownsampling. v3 (Ken): Dropped unnecessary memory context for "ralloc_asprintf()" Cc: "10.2" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Extend brw_get_rb_for_first_slice() for specified level/layerTopi Pohjolainen2014-05-152-7/+29
| | | | | | | | | | v2: Configure stencil directly for final dimensions instead of adjusting bit by bit for tiling, mip level and msaa. v3 (Ken): Used non-static constant for horizontal alignment Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8: Surface state overriding for stencilTopi Pohjolainen2014-05-151-13/+21
| | | | | | | | | | | | | | v2: Allow hardware to offset accesses to individual layers. Also leave the mip-level overriding for the creator of the intel renderbuffer to handle. Merged with "i965/gen8: Allow stencil buffers to be configured as single sampled" Ken: I left the "_mesa_problem()" still in place. I think it is clearer to remove it in a separate patch. Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/wm: Surface state overrides for configuring w-tiled as y-tiledTopi Pohjolainen2014-05-152-0/+30
| | | | | | | | | | v2: Use intel_mipmap_tree::total_width in order to get correct alignment automatically. Also use "mt->total_height / mt->physical_depth0" as surface height allowing hardware to offset to correct slice. Cc: "10.2" <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965 meta up/downsample: Fix renderbuffer _BaseFormatJordan Justen2014-05-151-1/+2
| | | | | | | | | | | | mt->format is of type mesa_format, and therefore can't be used with _mesa_base_fbo_format which requires a GLenum input. On gen8, this fixes various piglit fbo-depthstencil tests with samples > 1. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "10.2" <[email protected]>
* i965: Delete current_insn() function.Matt Turner2014-05-152-7/+2
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* i965: Remove blorp unit tests.Matt Turner2014-05-153-1099/+1
| | | | | | | | | They've served their purpose (in transitioning blorp to using fs_generator) and now they just necessitate large amounts of manual labor to regenerate if the disassembler changes. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* egl-static: include libradeonwinsys.la only onceEmil Velikov2014-05-151-8/+5
| | | | | | | | | | | With this and the previous patch, we no longer have multiple definitions in the final egl_gallium.so. v2: Drop duplicate libloader link. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Chia-I Wu <[email protected]> (v1) Reviewed-by: Tom Stellard <[email protected]> (v1)
* gallium/radeon: link in libradeon.la at target levelEmil Velikov2014-05-1512-20/+22
| | | | | | | | | | | | It makes more sense to link the core and common parts of the driver as the target is build. Additionally this will help us drop duplicating symbols for targets that static link mulitple pipe-drivers. Only egl-static needs that currently with more to come. To simplify things a bit add HAVE_GALLIUM_RADEON_COMMON variable. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* gallium/radeon: build only a single common library libradeonEmil Velikov2014-05-153-12/+5
| | | | | | | Just fold libllvmradeon in libradeon. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* freedreno/a3xx: fix write to bogus registerRob Clark2014-05-141-2/+2
| | | | | | | | | | | The loops for updating the multiple packed fields in SP_VS_OUT[] and SP_VS_VPC_DST[] will zero out one register beyond the last that on required. Which is normally not a problem (and is kinda convenient when looking at cmdstream dumps) unless we have maximum (16) varyings. Fix loop termination condition so that this does not happen. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: account for special inputs/outputsRob Clark2014-05-141-2/+2
| | | | | | | | | We need to size input/output tables big enough for special inputs/ outputs (gl_Position, gl_FrontFacing, etc) which, while they don't count towards the hw limit of 16 attributes or 16 varyings, we do still need to track them all the same. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix MAX_INPUTS shader capRob Clark2014-05-143-1/+9
| | | | | | | | | | Hardware only supports 16. Which fd3_shader_variant properly reflected, but the pipe cap did not, leading to array overflow (and shaders that could not possibly work). Also a bunch of asserts to make problems like this easier to see. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: add debug flag to expose glsl130Rob Clark2014-05-142-3/+8
| | | | | | | | | | We are starting to add integer support to the compiler, which does not get exercised with glsl feature level 120 and without advertising integer support. But doing so breaks too many things right now. So for now use a debug flag to conditionally expose the functionality while it is in development. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: add KILL_IFRyan Houdek2014-05-141-1/+35
| | | | | | | | | The KILL_IF opcode could potentially be merged in to the regular KILL opcode function. It was a pain to do so, so I've left is separated for cleanliness. Signed-off-by: Ryan Houdek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: start adding integer supportRyan Houdek2014-05-141-0/+169
| | | | | | | | | | | | | Adds a large sum of TGSI opcodes to the a3xx compiler. For integer opcodes we have 28 opcodes added. Adds 4 floating point compare opcodes If GLSL 1.30 is enabled, this allows the GLSL 1.30 piglits to have a completion amount of 432/641. Signed-off-by: Ryan Houdek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* draw: better llvm names for shaders for debugging.Roland Scheidegger2014-05-151-6/+12
| | | | | | | | All shaders had the same name. We could probably use some identifier per shader too, but for now only use the variant number. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: improve setup shader names (for debugging)Roland Scheidegger2014-05-151-38/+40
| | | | | | | | | | | | | The setup shaders were composed of both a fs shader number and a variant number. But since they aren't tied to a particular fragment shader, the former was a fixed zero while the latter was also always zero because it was never assigned. So, similar to what the fs code does, use a ever increasing number to give it a more catchy name (unlike fragment shaders though where this number is for each explicitly created shader, we just use it for the implicitly created variants). And while here, fix whitespace a bit. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: kill off llvmpipe_variant_countRoland Scheidegger2014-05-154-20/+4
| | | | | | | Unused except it was increased for both fs and setup shader variants created. Probably some leftover from ages ago. Reviewed-by: Jose Fonseca <[email protected]>
* mesa/st: fix number of ubos being declared in a shaderRoland Scheidegger2014-05-151-3/+5
| | | | | | | | | | | | Previously the code used the total number of ubos being declared in the linked program (so the ubos of all shaders combined), use the number from the particular shader instead. This fixes an assertion failure with piglit arb_uniform_buffer_object-maxblocks seen in llvmpipe since 8a9f5ecdb116d0449d63f7b94efbfa8b205d826f as it now emits code for each declared buffer, not just the ones actually used. CC: "10.1 10.2" <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0: enable support for maxwell boardsBen Skeggs2014-05-156-19/+49
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add maxwell (sm50) compiler backendBen Skeggs2014-05-1516-5/+3588
| | | | | | | | | | The big missing part here is proper sched data calculations, but hopefully the chosen placeholder will be sufficient for now. Passes piglit as well as GK107 does. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: maxwell isa has no per-instruction join modifierBen Skeggs2014-05-154-19/+23
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: replace immd 0 with $rLASTGPR for emit/restart opcodesBen Skeggs2014-05-151-0/+1
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: move nvc0 lowering pass class definitions into headerBen Skeggs2014-05-153-106/+136
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: bump sched data member to 32-bitsBen Skeggs2014-05-151-1/+1
| | | | | | | SM50 backend requires 21 bits per instruction, not 8. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: use vertex arrays for eng3d blitBen Skeggs2014-05-151-31/+64
| | | | | | | Maxwell doesn't have immediate-mode. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: restrict "constant vbo" logic to fermi/kepler classesBen Skeggs2014-05-151-1/+1
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: replace some vb->stride checks with constant_vbo insteadBen Skeggs2014-05-151-3/+3
| | | | | | | | Maxwell no longer has the methods to set constant attributes, and we'll want to be treating stride 0 vtxbufs the same as for stride > 0. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: add maxwell classBen Skeggs2014-05-152-0/+4
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: allow for easier modification of compiler library routinesBen Skeggs2014-05-1513-1057/+1057
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nvc0: properly distribute macros in source formBen Skeggs2014-05-155-244/+365
| | | | | Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* automake: Honor GL_LIB for gallium libgl-xlibBrad King2014-05-141-7/+7
| | | | | | | Use "@GL_LIB@" in src/gallium/targets/libgl-xlib/Makefile.am to produce the library name specified by the configure --with-gl-lib-name option. Reviewed-by: Emil Velikov <[email protected]>
* gallivm: only fetch pointers to constant buffers onceRoland Scheidegger2014-05-142-37/+65
| | | | | | | | | | | | | | | | | In 1d35f77228ad540a551a8e09e062b764a6e31f5e support for multiple constant buffers was introduced. This meant we had another indirection, and we did resolve the indirection for each constant buffer access. This looks very reasonable since llvm can figure out if it's the same pointer, however it turns out that this can cause llvm compilation time to go through the roof and beyond (I've seen cases in excess of factor 100, e.g. from 50 ms to more than 10 seconds (!)), with all the additional time spent in IR optimization passes (and in the end all of it in DominatorTree::dominate()). I've been unable to narrow it down a bit more (only some shaders seem affected, seemingly without much correlation to overall shader complexity or constant usage) but it is easily avoidable by doing the buffer lookups themeselves just once (at constant buffer declaration time). Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: fix output stream flushing in error case for disassembly.Roland Scheidegger2014-05-141-0/+5
| | | | | When there's an error, also need to flush the stream, otherwise an assertion is hit (meaning you don't actually see the error neither).
* radeonsi: Fix anisotropic filtering state setupMichel Dänzer2014-05-143-13/+12
| | | | | | | | | | | | Bring it back in line with r600g. I broke this in the original radeonsi bringup. :( Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78537 Cc: "10.1 10.2" <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* tgsi: support parsing texture offsets from text tgsi shadersIlia Mirkin2014-05-141-5/+48
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* mesa/st: provide native integers implementation of ir_unop_anyIlia Mirkin2014-05-141-24/+76
| | | | | | | | | | | Previously, ir_unop_any was implemented via a dot-product call, which uses floating point multiplication and addition. The multiplication was completely pointless, and the addition can just as well be done with an or. Since we know that the inputs are booleans, they must already be in canonical 0/~0 format, and the final SNE can also be avoided. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/docs: clarify when query results are resetRob Clark2014-05-141-0/+2
| | | | | | | | It wasn't completely clear from the docs, so I had to figure out by looking at piglit results. Hopefully this saves the next driver writer implementing queries some time. Signed-off-by: Rob Clark <[email protected]>
* gallivm: Remove lp_func_delete_body.José Fonseca2014-05-143-15/+0
| | | | | | | Not necessary, now that we will free the whole module (hence all function bodies) immediately after compiling. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Remove gallivm_free_function.José Fonseca2014-05-142-23/+0
| | | | | | Unused. Deprecated by gallivm_free_ir(). Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Delete unneeded LLVM stuff earlier.José Fonseca2014-05-147-34/+16
| | | | | | Same as Frank's change to draw module but for llvmpipe module. Reviewed-by: Roland Scheidegger <[email protected]>
* draw: Delete unneeded LLVM stuff earlier.Frank Henigman2014-05-141-15/+4
| | | | | | | | | | Free up unneeded LLVM stuff immediately after generating vertex shader code. Saves about 500K per shader. v2: Don't bother calling gallivm_free_function (Jose) Signed-off-by: José Fonseca <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
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