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* i965: Reverse condition ordering to let us support other gens.Matt Turner2014-08-181-3/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Add CSEL.Matt Turner2014-08-181-0/+1
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* mesa: fix copy and paste errors in glBindVertexBuffersTimothy Arceri2014-08-191-2/+2
| | | | | Signed-off-by: Timothy Arceri <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]>
* nv50/ir: (trivial) initialize pointer to silence warningTobias Klausmann2014-08-181-1/+1
| | | | | Reviewed-by: Ilia Mirkin <[email protected]> Signed-off-by: Tobias Klausmann <[email protected]>
* vc4: Add support for swizzling of texture colors.Eric Anholt2014-08-183-4/+39
| | | | | Fixes swapped colors on the copypix demo and some piglit tests like pbo-teximage-tiling .
* vc4: Fix handling of non-XYZW swizzles in color outputs.Eric Anholt2014-08-181-6/+6
| | | | | | | The SWIZZLE_1 of the winsys destination was dereffing off the end of the array, which surprisingly often worked out (since nobody reads the rendered value anyway, so whatever junk was referenced in the QIR didn't matter), but shader dumping would sometimes segfault.
* vc4: Extract the swizzle handling from vertex fetch.Eric Anholt2014-08-181-27/+32
| | | | | I want to reuse this elsewhere, and NONE debug output hasn't been useful so I don't miss it being as detailed as it was before.
* vc4: Add support for color masking.Eric Anholt2014-08-181-13/+24
| | | | | This gets fbo-colormask-formats working for core formats, which increases my confidence in some of the swizzle and blend handling.
* vc4: Add a helper for QOP_R4_UNPACK_[ABCD].Eric Anholt2014-08-182-8/+11
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* vc4: Don't forget to set up the offset for render targets.Eric Anholt2014-08-181-0/+2
| | | | | This almost fixes fbo-generatemipmap rendering, except that the 1x1 level isn't getting rendered.
* vc4: Fix multi-level texture setup.Eric Anholt2014-08-182-2/+12
| | | | | | | We weren't accounting for the level 0 offset in the texture setup (so it only worked if it happened to be a single-level texture), and doing so required that we get the level 0 offset page aligned so that the offset bits don't get interpreted as the texture format and such.
* vc4: Fix viewport handling in the uniforms upload.Eric Anholt2014-08-181-4/+2
| | | | | | | | | | | I had the right viewports in vc4_emit.c, but grabbed the wrong values in the uniform setup, so primitives would claim to be in the wrong parts of the screen. (The vc4_emit.c state looks like it just decides how big the clipping guardband is). This gets fbo-viewport closer to working (which still has the problem that the HW is always guard-band clipping), and fixes inverted FBO rendering in general.
* clover: Refuse to build a program if there are kernel objects attached to it.Francisco Jerez2014-08-185-3/+18
| | | | | | Fixes piglit cl-api-build-program. Tested-by: EdB <[email protected]>
* clover/util: Pass initial count value to ref_counter constructor.Francisco Jerez2014-08-181-2/+2
| | | | | | And mark the ref_count() method as const. Tested-by: EdB <[email protected]>
* clover/util: Implement minimalist reference to clover::ref_counter object.Francisco Jerez2014-08-181-0/+45
| | | | Tested-by: EdB <[email protected]>
* clover: clGetProgramInfo support for OpenCL 1.2.EdB2014-08-171-0/+11
| | | | | | | [ Francisco Jerez: Rework using fold() for conciseness. ] Reviewed-by: Francisco Jerez <[email protected]> Tested-by: EdB <[email protected]>
* nouveau: don't keep stale pointer to free'd dataIlia Mirkin2014-08-161-0/+1
| | | | | | | | | If ->sys is non-null, we might decide that it's where the data is stored. Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* egl: don't exit process on initialization failureIlia Mirkin2014-08-161-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* mesa: fix compressed_subtexture_error_check() return valueBrian Paul2014-08-161-3/+3
| | | | | | | | | The function should return GLboolean, not GLenum. If we detect invalid compressed pixel storage parameters, we should return GL_TRUE, not GL_FALSE so that the function is no-op'd. An update to the piglit s3tc-errors test will check this. Reviewed-by: Matt Turner <[email protected]>
* mesa: move _mesa_compressed_texture_pixel_storage_error_check()Brian Paul2014-08-165-46/+61
| | | | | | | to pixelstore.c, add const qualifier to the 'packing' parameter. Add comments. Reviewed-by: Matt Turner <[email protected]>
* mesa: minor improvements to _mesa_compute_compressed_pixelstore()Brian Paul2014-08-163-12/+23
| | | | | | | | | Replace the gl_texture_image parameter with mesa_format since we only used the image's format. Add some comments. Reviewed-by: Matt Turner <[email protected]>
* util: whitespace and formatting fixes in u_math.hBrian Paul2014-08-161-17/+23
| | | | Trivial.
* nouveau: make sure to invalidate any vbo state as wellIlia Mirkin2014-08-161-0/+1
| | | | | | Reviewed-by: Francisco Jerez <[email protected]> Signed-off-by: Ilia Mirkin <[email protected]> Cc: <[email protected]>
* i965/gen6: Force ALL_SLICES_AT_EACH_LOD for separate stencil/hizJordan Justen2014-08-151-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For gen6 we will use the ALL_SLICES_AT_EACH_LOD miptree layout for separate stencil/hiz. This is needed because gen6 hiz and separate stencil only support a single miplevel. When accessing the other LODs, we will program a tile aligned offset for the bo. PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." We still allocate storage for the other stencil mip-levels within a single texture, but each mip-level will use non-mip-array spacing. PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." We allocate storage for the other hiz mip-levels within a single texture, but each mip-level will use non-mip-array spacing. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Stencil/hiz needs an offset for LOD > 0Jordan Justen2014-08-152-3/+41
| | | | | | | | | | | | Since gen6 separate stencil & hiz only supports LOD0, we need to program an offset to the LOD when emitting the separate stencil/hiz. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6: Force tile alignment for each stencil/hiz LODJordan Justen2014-08-151-3/+36
| | | | | | | | | | | | | | | | Gen6 doesn't support multiple miplevels for hiz and stencil. Therefore, we must point to the LOD directly during rendering. But, we also have removed the tile offsets from normal depth surfaces, so we need to align each LOD to a tile boundary for hiz and stencil. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Support array_layout == ALL_SLICES_AT_EACH_LOD for multiple LODsJordan Justen2014-08-151-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously array_layout ALL_SLICES_AT_EACH_LOD was only used for array spacing lod0 on gen7+ and therefore was only used with a single mip level. gen6 separate stencil & hiz only support LOD0, so we need to allocate the miptree similar to gen7+ array spacing lod0, except we also need space for multiple mip levels. (Since OpenGL stencil and depth support multiple LODs.) The miptree is allocated with tightly packed array slice spacing, but we still also pack the miplevels into the region similar to a normal multi mip level packing. A 2D Array texture with 2 slices and multiple LODs would look somewhat like this: +----------+ | | | | +----------+ | | | | +----------+ +---+ +-+ | | +-+ +---+ +-+ | | : +---+ v3: * Use new array_layout enum * ASCII art! Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LODJordan Justen2014-08-157-17/+35
| | | | | | | | | | | | | gen6 does not support multiple miplevels with separate stencil/hiz. Therefore we need to layout its miptree with no mipmap spacing between the slices of each miplevel. v3: * Use new array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: Change mipmap array_spacing_lod0 to array_layout (enum)Jordan Justen2014-08-157-19/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will want to setup gen6 separate stencil and hiz miptrees in a layout that is similar to array_spacing_lod0. This is needed because gen6 hiz and stencil only support a single mip-level. In both use cases (gen7+ LOD0 spacing & gen6 separate stencil/hiz), the array slices will be packed at each LOD without reserving extra space for LODs within each array slice. So, we generalize the name of this field and add comments to indicate the old and new uses. Motivation for the gen6 change comes from the PRM: PRM Volume 1, Part 1, 7.18.3.7.2 For separate stencil buffer [DevILK] to [DevSNB]: "The separate stencil buffer does not support mip mapping, thus the storage for LODs other than LOD 0 is not needed." PRM Volume 2, Part 1, 7.5.3 Hierarchical Depth Buffer "[DevSNB]: The hierarchical depth buffer does not support the LOD field, it is assumed by hardware to be zero. A separate hierarachical depth buffer is required for each LOD used, and the corresponding buffer’s state delivered to hardware each time a new depth buffer state with modified LOD is delivered." v2: * Rename array_spacing_lod0 to non_mip_arrays v3: * Instead, replace array_spacing_lod0 with array_layout enum Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2014-08-153-59/+51
| | | | | | | | | | | | | | | | | | | | | | (bf25ee2 for gen6) Previously we would always find the 2D sub-surface of interest, and then program the surface to this location. Now we always program the 3DSTATE_DEPTH_BUFFER at the start of the surface. To select the lod/slice, we utilize the lod & minimum array element fields. We also must disable brw_workaround_depthstencil_alignment for gen >= 6. Now the hardware will handle alignment when rendering to additional slices/LODs. v3: * Set depth_mt bo RELOC offset to 0, as was done in bf25ee2 Signed-off-by: Jordan Justen <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=56127 Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6 fbo: make unmatched depth/stencil configs return unsupportedJordan Justen2014-08-151-3/+3
| | | | | | | | (f3c886b for gen6) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 blorp depth: calculate base surface width/heightJordan Justen2014-08-151-0/+13
| | | | | | | | | | (e3a49e1 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate minimum array element being renderedJordan Justen2014-08-152-0/+4
| | | | | | | | | | | (a23cfb8 for gen6) In layered rendering this will be 0. Otherwise it will be the selected slice. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate LOD being rendered toJordan Justen2014-08-152-0/+6
| | | | | | | | | | (08ef1dd for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate depth (array size) for depth surfaceJordan Justen2014-08-152-0/+5
| | | | | | | | | | | | | (bc1acaa for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6 depth surface: calculate more specific surface typeJordan Justen2014-08-152-0/+50
| | | | | | | | | | | | | (171e633 for gen6) This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Note: Cube maps are treated as 2D arrays with 6 times as many array elements as the cube map array would have. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6_depth_state.c: Remove (gen != 6) code pathsJordan Justen2014-08-151-31/+14
| | | | | | | | | Since this code was branched from brw_misc_state.c, it had support for gen != 6. We can now remove this. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split gen6 depth hiz state out from brwJordan Justen2014-08-154-1/+188
| | | | | | | | | | | | We will program the gen6 hiz depth state differently to enable layered rendering on gen6. v2: * Remove unneeded gen6_emit_depthbuffer as suggested by Topi Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Adjust render height in errata case for MSAAJordan Justen2014-08-151-1/+17
| | | | | | | | | | | | | | | | | | | In the gen6 PRM Volume 1 Part 1: Graphics Core, Section 7.18.3.7.1 (Surface Arrays For all surfaces other than separate stencil buffer): "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than the value calculated in the equation above , for every other odd Surface Height starting from 1 i.e. 1,5,9,13" Since this Qpitch errata only impacts the sampler, we have to adjust the input for the rendering surface to achieve the same qpitch. For the affected heights, we increment the height by 1 for the rendering surface. Signed-off-by: Jordan Justen <[email protected]> Acked-by: Chris Forbes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6: Add support for layered renderbuffersJordan Justen2014-08-152-40/+43
| | | | | | | | | | | | | | | | | | | | | | Rather than pointing the surface_state directly at a single sub-image of the texture for rendering, we now point the surface_state at the top level of the texture, and configure the surface_state as needed based on this. v2: * Use SET_FIELD as suggested by Topi * Simplify min_array_element assignment as suggested by Topi v3: * Use irb->layer_count for depth instead of rb->Depth * Make gl_target const * depth - 1, not depth v4: * Merge in dd43900b & b875f39e fixes to prevent 3D texture piglit regressions Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6_surface_state.c: Remove (gen < 6) code pathJordan Justen2014-08-151-22/+0
| | | | | | | | Since this code was branched from brw_wm_surface_state.c, it had support for gen < 6. We can now remove this. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split gen6 renderbuffer surface state from gen5 and olderJordan Justen2014-08-154-0/+159
| | | | | | | | | We will program the gen6 renderbuffer surface state differently to enable layered rendering on gen6. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* meta: Use instanced rendering for layered clears.Kenneth Graunke2014-08-151-16/+5
| | | | | | | | | Layered rendering is part of OpenGL 3.2; GL_ARB_draw_instanced is part of OpenGL 3.1. As such, all drivers supporting layered rendering already support gl_InstanceID. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* mesa: Expose vbo_exec_DrawArraysInstanced as _mesa_DrawArraysInstanced.Kenneth Graunke2014-08-152-0/+10
| | | | | | | So we can use it in meta.c. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* Revert "hud: don't overrun malloced arrays"Dave Airlie2014-08-161-1/+0
| | | | | | | | | This reverts commit 1cfcd0164e1be7d7b05b693f60a262ad735b7565. This seems to cause r600g lockups, https://bugs.freedesktop.org/show_bug.cgi?id=82628 Signed-off-by: Dave Airlie <[email protected]>
* i965: Guard access to gl_Layer by extension #ifdefKristian Høgsberg2014-08-151-0/+2
| | | | | | | | | | | Only assign gl_Layer if we have GL_AMD_vertex_shader_layer. Gen6 doesn't (currently) have that extension, but it also doesn't support layered rendering. Signed-off-by: Kristian Høgsberg <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Tested-by: Jordan Justen <[email protected]>
* gallium/vc4: PIPE_CAP_VIDEO_MEMORY return the amount of system ramEmil Velikov2014-08-151-3/+9
| | | | | | Suggested-by: Eric Anholt <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Add support for blending.Eric Anholt2014-08-155-12/+199
| | | | | | | | Passes blendminmax and blendsquare. glean's more serious blendFunc fails in simulation due to binner memory overflow (I really need to work around that), and fbo-blending-formats fails due to Mesa refusing one of the getter requests, even before it could fail due to the driver not actually supporting different formats yet.
* vc4: Drop incorrect attempt to incorrectly invert the primconvert hw_mask.Eric Anholt2014-08-151-1/+1
| | | | | | | | The hw_mask is the set of primitives you actually support, so this attempt to provide the set of formats that's unsupported was wrong in two ways (it was intended to be '~' not '!'). However, we only call this code when prim isn't one of the actually supported hw_mask bits, so missing out on the memcpy didn't matter anyway.
* vc4: Use cl_f() instead of cl_u32(fui())Eric Anholt2014-08-151-6/+6
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