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* ilo: add image_init_gen6_transfer_layout()Chia-I Wu2015-07-011-75/+37
* ilo: add image_set_gen6_bo_size()Chia-I Wu2015-07-013-118/+89
* ilo: add image_set_gen6_{hiz,mcs}Chia-I Wu2015-07-011-49/+61
* ilo: add image_get_gen6_monolithic_size()Chia-I Wu2015-07-011-67/+67
* ilo: add image_get_gen6_lods()Chia-I Wu2015-07-011-88/+148
* ilo: add image_get_gen{6,7}_alignment()Chia-I Wu2015-07-011-159/+177
* ilo: add image_get_gen6_{hiz,mcs}_enable()Chia-I Wu2015-07-011-101/+97
* ilo: add image_get_gen6_tiling()Chia-I Wu2015-07-011-132/+177
* ilo: add image_get_gen6_layout()Chia-I Wu2015-07-011-82/+107
* nv50/ir: copy joinAt when splitting both before and afterIlia Mirkin2015-07-013-0/+5
* gallivm: add fp64 support. (v2.1)Dave Airlie2015-07-018-31/+553
* tgsi: add infer support for double opcodes.Dave Airlie2015-07-011-0/+37
* freedreno: use consistent version string formatTimothy Arceri2015-07-011-1/+1
* glsl: use consistent version string formatTimothy Arceri2015-07-011-7/+7
* i965/fs: Fix PIXEL_X/Y in regs_read()Jason Ekstrand2015-06-301-1/+1
* i965/fs: Remove the width field from fs_regJason Ekstrand2015-06-308-107/+30
* i965/fs_generator: Use inst->exec_size for determining hardware reg widthsJason Ekstrand2015-06-301-7/+7
* i965/fs: Use exec_size instead of dst.width for computing component sizeJason Ekstrand2015-06-305-8/+8
* i965/fs: Use the builder dispatch_width for computing register offsetsJason Ekstrand2015-06-301-1/+1
* i965/fs: Use the builder dispatch width instead of dst.width for pull constantsJason Ekstrand2015-06-301-4/+4
* i965/fs: Remove exec_size guessing from fs_inst::init()Jason Ekstrand2015-06-301-22/+0
* i965/fs_builder: Use the dispatch width for setting exec sizesJason Ekstrand2015-06-301-9/+11
* i965/fs: Use exec_size for determining regs read/written and partial writesJason Ekstrand2015-06-301-3/+3
* i965/fs: Remove fs_inst constructors that don't take an explicit exec_sizeJason Ekstrand2015-06-304-39/+8
* i965/fs: Make better use of the builder in shader_timeJason Ekstrand2015-06-301-6/+8
* i965/fs: Add a builder argument to offset()Jason Ekstrand2015-06-307-123/+132
* i965/fs: Move offset(fs_reg, unsigned) to brw_fs.hJason Ekstrand2015-06-302-21/+21
* i965/blorp: Explicitly set execution sizes for new'd instructionsJason Ekstrand2015-06-301-4/+5
* i965/fs: Set the builder group for emitting FB-write stencil/AA alphaJason Ekstrand2015-06-301-1/+1
* i965/fs: Explicitly set the exec_size on the add(32) in interpolation setupJason Ekstrand2015-06-301-4/+6
* i965/fs: Properly handle LOAD_PAYLOAD in fs_inst::regs_readJason Ekstrand2015-06-301-0/+5
* i965/fs: Report the right value in fs_inst::regs_read() for PIXEL_X/YJason Ekstrand2015-06-301-2/+9
* i965/fs: Fix fs_inst::regs_read() for uniform pull constant loadsJason Ekstrand2015-06-301-0/+6
* i965/fs: Actually set/use the mlen for gen7 uniform pull constant loadsJason Ekstrand2015-06-302-13/+15
* i965/fs: Use a switch statement in fs_inst::regs_read()Jason Ekstrand2015-06-301-22/+23
* nir: remove parent_instr from nir_registerConnor Abbott2015-06-303-17/+0
* nir: remove nir_src_get_parent_instr()Connor Abbott2015-06-301-10/+0
* i965/fs: emit constants only onceConnor Abbott2015-06-302-13/+16
* i965/fs: use SSA values directlyConnor Abbott2015-06-305-30/+52
* nir/from_ssa: add a flag to not convert everything from SSAConnor Abbott2015-06-304-10/+26
* egl/x11: handle when invalid drawable is passed in create_surfaceEmil Velikov2015-06-301-0/+4
* egl/wayland: cleanup dri2_wl_create_surface error pathEmil Velikov2015-06-301-3/+1
* egl/wayland: handle NULL native_window in create_surfaceEmil Velikov2015-06-301-0/+5
* egl/drm: plug memory leakEmil Velikov2015-06-301-2/+5
* gallium/ttn: don't upset nir_validate w/ BRK'sRob Clark2015-06-301-1/+1
* gallium/ttn: add TXB2Rob Clark2015-06-301-0/+11
* gallium/ttn: partial fix for output arraysRob Clark2015-06-301-2/+4
* nir: cleanup open-coded instruction castsRob Clark2015-06-303-3/+3
* freedreno/ir3: cache defining instructionRob Clark2015-06-303-69/+91
* freedreno/ir3: fix RA issue with faninRob Clark2015-06-301-5/+15
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