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* Merge branch 'arb_map_buffer_range'Brian Paul2009-06-1522-4231/+4677
|\ | | | | | | | | | | | | Conflicts: docs/relnotes-7.6.html src/mesa/main/mtypes.h
| * st/mesa: enable GL_ARB_map_buffer_rangeBrian Paul2009-06-081-0/+1
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| * mesa: implement GL_ARB_map_buffer_rangeBrian Paul2009-06-088-13/+265
| | | | | | | | | | | | | | | | | | | | Only enabled for software drivers at this point. Note that the gl_buffer_object::Access enum field has been replaced by a gl_buffer_object::AccessFlags bitfield. The new field is a mask of the GL_MAP_x_BIT flags which is a superset of the old GL_READ_ONLY, GL_WRITE_ONLY and GL_READ_WRITE modes. When we query GL_BUFFER_ACCESS_ARB we translate the bitfield into the conventional enum values.
| * mesa: regenerated files for GL_ARB_map_buffer_rangeBrian Paul2009-06-0810-4218/+4374
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| * glapi: hook in ARB_map_buffer_range.xmlBrian Paul2009-06-082-0/+3
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| * glapi: spec/xml file for GL_ARB_map_buffer_rangeBrian Paul2009-06-081-0/+34
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| * mesa: reorder fields, update comments for gl_buffer_objectBrian Paul2009-06-081-8/+11
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* | mesa: revert some recent VBO buffer object refcounting changesBrian Paul2009-06-152-8/+3
| | | | | | | | | | | | | | | | Reverts part of commit d7ea9ddf5824556e47decac7ba200f37cf1e552f. We were calling _mesa_reference_buffer_object() on some heap-allocated memory that was uninitialized and could trigger an assertion. We can actually go back to "looser" ref counting of the Null/default buffer object in these cases.
* | enable ARB_half_float_pixel for intel driversRoland Scheidegger2009-06-151-0/+1
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* | intel: fix (cosmetic) typo flag used twiceRoland Scheidegger2009-06-151-1/+0
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* | Merge branch 'mesa_7_5_branch'Thomas Hellstrom2009-06-151-1/+5
|\ \ | | | | | | | | | | | | | | | Conflicts: progs/util/extfuncs.h
| * | gallium: Fix segfault and valgrind error introduced with commit ↵Thomas Hellstrom2009-06-151-1/+5
| | | | | | | | | | | | | | | | | | 3f2e006b759705abd7c409d30f9aeb1f2a75b83f Signed-off-by: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
* | | r300: fix 3D texturesMaciej Cencora2009-06-151-1/+20
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* | | i965: interpolate colors with perspective correction by defaultBrian Paul2009-06-126-13/+38
| | | | | | | | | | | | | | | | | | | | | ...rather than with linear interpolation. Modern hardware should use perspective-corrected interpolation for colors (as for texcoords). glHint(GL_PERSPECTIVE_CORRECTION_HINT, mode) can be used to get linear interpolation if mode = GL_FASTEST.
* | | mesa: use larger initial refcount for NullBufferObjBrian Paul2009-06-121-1/+1
| | | | | | | | | | | | | | | Refcounting of the null/default buffer object isn't perfect yet so be extra safe.
* | | mesa: use _mesa_reference_buffer_object() in a few placesBrian Paul2009-06-121-5/+9
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* | | mesa: use _mesa_reference_buffer_object() in a few placesBrian Paul2009-06-123-4/+10
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* | | r300: add support for EXT_texture_sRGBMaciej Cencora2009-06-124-0/+27
| | | | | | | | | | | | Tested with glean/texture_srgb and wine/d3d9 tests on RV535
* | | set/mesa: enable GL_NV_texture_env_combine4Brian Paul2009-06-121-0/+1
| | | | | | | | | | | | | | | This is handled entirely in core Mesa where the combiner state is converted into a fragment program.
* | | st/mesa: additional debug code (disabled)Brian Paul2009-06-121-0/+20
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* | | Merge branch 'mesa_7_5_branch'Jakob Bornecrantz2009-06-127-35/+125
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| * | mesa: Enable uploads of only depth to z24s8 texturesJakob Bornecrantz2009-06-121-3/+36
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| * | mesa: rework vertex shader output / fragment shader input attribute matchingBrian Paul2009-06-111-20/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before, if a vertex shader's outputs didn't exactly match a fragment shader's inputs we could wind up with invalid TGSI shader declarations. For example: Before patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[0] <- note duplicate [0] DCL OUT[4], GENERIC[2] After patch: DCL OUT[0], POSITION DCL OUT[1], COLOR[1] DCL OUT[2], GENERIC[0] DCL OUT[3], GENERIC[1] DCL OUT[4], GENERIC[2]
| * | mesa: add default function for ctx->Driver.CheckQuery() hookBrian Paul2009-06-113-1/+19
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| * | python/retrace: Show the contents of the depth/stencil and surfaces ↵José Fonseca2009-06-111-10/+28
| | | | | | | | | | | | before/after transfers.
| * | python/retrace: Interpret is_texture_referenced/is_buffer_referenced.José Fonseca2009-06-111-0/+8
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| * | wgl: Fix prototype.José Fonseca2009-06-111-1/+1
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* | | Disable SGI_swap_control extension for DRI2Owen W. Taylor2009-06-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | We currently don't have support for SGI_swap_control for direct contexts with DRI2, so disable reporting the extension. Reporting the extension, and then having glXSwapIntervalSGI() "succeed" but do nothing can confuse applications. https://bugs.freedesktop.org/show_bug.cgi?id=22123
* | | radeon: fix size of mipmap texture arrayDave Airlie2009-06-121-1/+3
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* | | radeon/r200/r300: fix max texture levels assertDave Airlie2009-06-122-6/+3
| | | | | | | | | | | | use the actual value set in the context
* | | Merge remote branch 'main/radeon-rewrite'Dave Airlie2009-06-12118-18854/+16421
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| * | | r300: fix VAP setupMaciej Cencora2009-06-111-5/+6
| | | | | | | | | | | | | | | | If GL context had e.g. tex0, tex2 and fog the VAPOutputCntl1 returned 0x104 instead of 0x124 - that meaned we're sending only 8 texcoords (instead of 12) which ended up in GPU hang.
| * | | r300: fix for SW TCL pathMaciej Cencora2009-06-111-1/+1
| | | | | | | | | | | | | | | | | | | | We shouldn't use i variable for SWTCL_OVM_TEX because textures doesn't have to be enabled in "packed" order. We could have tex1,tex3 and fog which would receive 7,9,8 OVM locations instead of 6,7,8.
| * | | r300: don't send unused attributes for SW TCL pathMaciej Cencora2009-06-111-14/+14
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| * | | r300: send only RS_IP_* regs that we are going to useMaciej Cencora2009-06-112-10/+4
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| * | | r300: fix RS setup when no colors and textures are sent to FPMaciej Cencora2009-06-111-4/+6
| | | | | | | | | | | | | | | | RS_COL_FMT field is part of RS_IP_* reg not RS_INST_*
| * | | r300: r500 fragment program fixesMaciej Cencora2009-06-111-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - when rewriting per component negate swizzle, first instruction should get not negated source - KIL instruction ignores swizzles TODO: - tex instructions does not support saturation - tex instructions cannot read from consant memory
| * | | radeon: increase max bo countMaciej Cencora2009-06-111-1/+1
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| * | | r300: fix a GPU lock upMaciej Cencora2009-06-113-21/+24
| | | | | | | | | | | | | | | | | | | | | | | | Sending from VAP more texture coordinates than RS expects results in GPU hang. Fixes BumpSelfShadow from DirectX8 SDK.
| * | | r300: fix vertex program bugMaciej Cencora2009-06-111-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | If the vertex program didn't write position attribute, the position invariant function would add necessary instructions, but the vertex position would be overwritten by artificial outputs insts added to satisfy fragment program requirements. Fixes "whole screen is gray" problem for HW TCL path in sauerbraten when shaders are enabled, and whole slew of wine d3d9 tests.
| * | | r300: move some code for easier debuggingMaciej Cencora2009-06-111-17/+37
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| * | | r300: print vertex program when debugging is enabledMaciej Cencora2009-06-111-3/+14
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| * | | r300: fix output register allocation for vertex shadersMaciej Cencora2009-06-111-9/+19
| | | | | | | | | | | | | | | | If the vertex program wrote secondary color without primary color, the secondary color output register index would be 0 which resulted in overwriting vertex position in some cases.
| * | | r300: hw doesn't support saturation for tex instructionsMaciej Cencora2009-06-111-0/+3
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| * | | r300: fix indexed primitive rendering when using memory managerJerome Glisse2009-06-111-2/+2
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| * | | r300: make sure indexed rendering doesn't try to use more than the num of ↵Jerome Glisse2009-06-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | vertices When with memory manager we need to make sure the GPU won't try to access beyond vertex buffer size, do so by enforcing that the maximun index is the last vertex of the buffer.
| * | | radeon: fix mipmap_limits crasher.Dave Airlie2009-06-091-1/+1
| | | | | | | | | | | | | | | | This gets the correct srclvl image map when uploading images to the new mipmap.
| * | | r300: fix regression caused by 056bc77547c304021a0faf204897ed238a5cf424Maciej Cencora2009-06-081-0/+1
| | | | | | | | | | | | | | | | Fixes GPU hangs in software TCL path
| * | | Merge remote branch 'origin/master' into radeon-rewriteDave Airlie2009-06-07261-7753/+14655
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| * | | | r300: Endianness fixes for recent vertex path changes.Michel Dänzer2009-06-072-9/+37
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Maciej Cencora <[email protected]>
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