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* svga: use pipe_sampler_view_release() to avoid segfaultBrian Paul2012-02-231-2/+6
| | | | | | | This fixes another case of faulting when freeing a pipe_sampler_view that belongs to a previously destroyed context. Reviewed-by: Jose Fonseca <[email protected]>
* st/wgl: check for hPbuffer=0 in wgl pbuffer functionsBrian Paul2012-02-231-0/+20
| | | | | | | Per the GL_WGL_pbuffer spec, generate ERROR_INVALID_HANDLE and return FALSE (and don't segfault). Reviewed-by: Jose Fonseca <[email protected]>
* st/wgl: Fix argument of stw_pixelformat_get_info().José Fonseca2012-02-231-1/+1
| | | | | stw_pixelformat_get_info takes zero based index, not a 1 based pixel format number.
* st/mesa: use pipe_sampler_view_release()Brian Paul2012-02-231-13/+5
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* gallium: added pipe_sampler_view_release() functionBrian Paul2012-02-231-0/+22
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: add floating point formats in st_new_renderbuffer_fb()Brian Paul2012-02-231-1/+8
| | | | | | To allow creating floating point buffers / pbuffers. Reviewed-by: Jose Fonseca <[email protected]>
* svga: re-enable deleted surface cachingBrian Paul2012-02-231-2/+1
| | | | | | | | Basically, instead of immediately freeing deleted surfaces, hang onto them in a cache to do quick re-allocation. This helps when surfaces are frequently destroyed and then reallocated a bit later. Reviewed-by: José Fonseca <[email protected]>
* svga: implement surface cache size limitBrian Paul2012-02-232-3/+137
| | | | | | | | | | | | | There was a SVGA_HOST_SURFACE_CACHE_BYTES symbol, but it was never used. Now when we go to add a newly deleted surface to the cache we check if the cache size would be exceeded. If so, try to free the least recently "unused" surfaces until the cache is smaller. If we can't do that, simply don't cache the newly deleted surface. The alternative involves flushing and waiting and we don't want to do that. Reviewed-by: José Fonseca <[email protected]>
* svga: add svga_format_size() functionBrian Paul2012-02-232-0/+163
| | | | Reviewed-by: José Fonseca <[email protected]>
* svga: use dummy shaders when translation failsBrian Paul2012-02-232-4/+95
| | | | | | | | | Before, if shader translation failed for any reason we'd keep trying to translate the shader over and over again during state validation. The dummy fragment shader emits solid red so that might be visual clue that translation is failing. Reviewed-by: Jose Fonseca <[email protected]>
* svga: move temp register index assertionsBrian Paul2012-02-232-6/+17
| | | | | | | | | | | | | | The assertion recently added in dst_register() was invalid because that function is also (suprisingly) used to declare constant registers. Move the assertion to the callers where we're really creating temp registers and add some code to prevent emitting invalid temp register indexes for release builds. Also, update the comment for get_temp(). It didn't return -1 if it ran out of registers and none of the callers checked for that. Reviewed-by: Jose Fonseca <[email protected]>
* svga: check that we don't exceed temp register limitBrian Paul2012-02-232-0/+6
| | | | | | | And assert on the register index in dst_register(). The dest can only be an output or temp reg and there's more of the later. Reviewed-by: Jose Fonseca <[email protected]>
* Add a test for the compare opcode.Alex Corscadden2012-02-231-0/+12
| | | | | This is a test for the compare opcode (CMP). This should draw a green triangle in the fs-test.
* r600g: Fix build when libdrm is installed to non-standard dir.Satyajit Sarangi2012-02-221-0/+3
| | | | | Signed-off-by: Satyajit Sarangi<[email protected]> Signed-off-by: Tom Stellard <[email protected]>
* i915: Initialize swrast_texture_image structure fields.Paul Berry2012-02-223-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 980f6f1 (mesa: move gl_texture_image::Width/Height/DepthScale fields to swrast) moved the initialization of the Width, Height, and DepthScale fields to _swrast_alloc_texture_image_buffer(). However, i915 doesn't call this function because it performs its own buffer allocation. As a result, the Width, Height, and DepthScale fields weren't getting initialized properly, and some operations requiring swrast would fail. This patch ensures that Width, Height, and DepthScale are properly initialized by separating the code that sets them into a new function, _swrast_init_texture_image(), which is called by intel_alloc_texture_image_buffer() as well as _swrast_alloc_texture_image_buffer(). It also moves the initialization of _IsPowerOfTwo into this function. Fixes piglit test fbo/fbo-cubemap on i915. Partially fixes https://bugs.freedesktop.org/show_bug.cgi?id=41216 This is a candidate for the 8.0 branch. Reviewed-and-tested-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: bump DRI_IMAGE extension version to 3Jesse Barnes2012-02-221-1/+1
| | | | | | | To indicate support for the format query. Reviewed-by: Kristian Høgsberg <[email protected]> Signed-off-by: Jesse Barnes <[email protected]>
* gbm: track buffer format through DRI driversJesse Barnes2012-02-2210-5/+179
| | | | | | | | | | | | GBM needs the buffer format in order to communicate with DRM and clients for things like scanout. So track the DRI format requested in the various back ends and use it to return the DRI format back to GBM when requested. GBM will then map this into the GBM surface type (which is in turn based on the DRM fb format list). Signed-off-by: Jesse Barnes <[email protected]>
* tests/graw: Add a bunch of tests.José Fonseca2012-02-2210-372/+1794
| | | | | | | | These were rotting in an internal branch, but contain nothing confidential, and would be much more useful if kept up-to-date with latest gallium interface changes. Several authors including Keith Whitwell, Zack Rusin, and Brian Paul.
* mesa: add special case in texstore.c for GL_LUMINANCE_ALPHA src imageBrian Paul2012-02-221-0/+26
| | | | | | About a 10% improvement over the swizzle-copy path. Reviewed-by: Jose Fonseca <[email protected]>
* gallium/cso: Put the comment about shader in the code for future reference.José Fonseca2012-02-221-0/+7
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* i965/gen6: Fix near-NULL deref in setting up GS binding table for non-XFB.Eric Anholt2012-02-211-5/+8
| | | | | Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Kenneth Graunke <[email protected]>
* i965: Correct the size of the state batch space allocated for binding tables.Eric Anholt2012-02-212-2/+2
| | | | | | | | | In the gen6 GS case, we were under-counting and so other state would get smashed. In the VS case, we were over-counting, so everything was fine. Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Kenneth Graunke <[email protected]>
* i965: Fix a bad comment in gen6 sol setup.Eric Anholt2012-02-211-3/+1
| | | | | | | | | This was copy and paste from the VS where I had similar code. We're only looking at things derived from BRW_NEW_VERTEX_PROGRAM in this block. Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Kenneth Graunke <[email protected]>
* i965/gen6: Fix the size of the GS surface binding table.Eric Anholt2012-02-211-1/+1
| | | | | | | I obviously didn't test on gen6 before pushing. Reviewed-by: Kenneth Graunke <[email protected]> Tested-by: Kenneth Graunke <[email protected]>
* r600g: move invariant register updates into start_cs for evergreen and caymanMarek Olšák2012-02-213-118/+100
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* r600g: move invariant register updates into start_cs for r6xx-r7xxMarek Olšák2012-02-213-102/+82
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* r600g: add a depth misc state which depends on occlusion queriesMarek Olšák2012-02-2110-91/+152
| | | | | | | | | | | | | | | | This is a state which is derived from other states and is actually the first state which doesn't correspond to any gallium state. There are two state flags: bool occlusion_query_enabled bool flush_depthstencil_enabled Additional flags can be added later if needed, e.g. bool hiz_enabled. The emit function will have to figure out the register values by itself. It basically just emits the registers when the state changes. This commit also adds a few helper functions for writing registers directly into a command stream.
* r600g: consolidate the main draw codeMarek Olšák2012-02-214-133/+50
| | | | | The code was almost the same for r600 and eg. What can't be consolidated is in the *_prepare functions.
* r600g: move all invariant state from draw_vbo into start_csMarek Olšák2012-02-217-20/+35
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* r600g: turn init_config into a command buffer for starting a CSMarek Olšák2012-02-2110-479/+379
| | | | | | | | | | | This is the first pure command buffer. It contains CS initialization packets and emits invariant state (i.e. the registers which never or rarely change). The affected registers are removed from *_hw_context.c, so that both ways of emitting commands can co-exist. v2: emit context_control in cayman's start_cs too
* i965: Only set Last Render Target Select on the last FB write.Kenneth Graunke2012-02-211-1/+1
| | | | | | | | | | | | | Fixes GPU hangs in OilRush, Trine, and Amnesia: The Dark Descent, which all use MRT (multiple render targets). NOTE: This is a candidate for release branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38720 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=40059 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45216 Reviewed-by: Eric Anholt <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* gallium/cso: kill off non-functional shader cachingMarek Olšák2012-02-214-171/+0
| | | | | | | | | Suggested by José. We don't provide shader caching in CSO. Most of the time the api provides object semantics for shaders anyway, and the cases where it doesn't (eg mesa's internall-generated texenv programs), it will be up to the state tracker to implement their own specialized caching.
* gallium/util: remove u_simple_screenMarek Olšák2012-02-213-182/+0
| | | | Deprecated and unused.
* gallium: remove unused winsys pointers in pipe_screen and pipe_contextMarek Olšák2012-02-2121-37/+0
| | | | A winsys is already a private object of a driver.
* intel: Silence valgrind warning for getparam ioctl argument.Eric Anholt2012-02-211-0/+1
| | | | It was concerned that the 4 pad bytes on LP64 were uninitialized.
* i965: Rename the original binding table to mention that it's the WM now.Eric Anholt2012-02-217-32/+30
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split the gen6 GS binding table to a separate table.Eric Anholt2012-02-215-10/+75
| | | | | | | | Improves VS state change microbenchmark performance by 7.08729% +/- 1.22289% (n=10) on gen7, because we don't upload the 64 dwords of unused binding table any more. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Split the VS binding table to a separate table.Eric Anholt2012-02-219-17/+94
| | | | | | | | This is a step toward making the samplers/binding tables reflect sampler uniform mappings instead of embedding those in the programs. No significant performance difference on the microbenchmark (n=10). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Avoid recomputing whether we use noperspective.Eric Anholt2012-02-213-36/+10
| | | | | | | Improves VS state change microbenchmark performance 2.38246% +/- 1.15046% (n=20). Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen7: Skip checking if we need a GS program for now.Eric Anholt2012-02-211-1/+0
| | | | | | | We always say no. Improves VS state change microbenchmark performance 7.68747% +/- 1.40826% (n=10). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Compute required barycentric interp modes once at FS compile time.Eric Anholt2012-02-214-20/+17
| | | | | | | Improves VS state change microbenchmark performance 1.78817% +/- 0.556878% (n=25). Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move VUE map computation to once at VS compile time.Eric Anholt2012-02-2112-49/+42
| | | | | | | | | | With this and the previous patch, 640x480 nexuiz is running 0.169118% +/- 0.0863696% faster (n=121). On a VS state change microbenchmark, performance is increased 8.28645% +/- 0.460478% (n=52). v2: Fix CACHE_NEW_VS comment. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make the userclip flag for the VUE map come from VS prog data.Eric Anholt2012-02-2110-39/+29
| | | | | | | | This reduces recomputation of state based on non-clipping-related transform changes, and is a step toward removing VUE map recomputation. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: fix issues with texture border and array texturesAnuj Phogat2012-02-211-11/+59
| | | | | | | | | | | For a 1D texture array, the border only applies to the width. For a 2D texture array the border applies to the width and height but not the depth. Sucha cases were not handled correctly in _mesa_init_teximage_fields(). Note: This is a candidate for stable branches Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon/r600g: fix virtual address space allocationJerome Glisse2012-02-211-0/+3
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* llvmpipe: Remove lp_test_sincos.José Fonseca2012-02-216-909/+8
| | | | Completely replaced by lp_test_arit.
* vl: add support for bob deinterlacingChristian König2012-02-214-12/+66
| | | | | | | v2: return VDP_STATUS_INVALID_VIDEO_MIXER_PICTURE_STRUCTURE for unknown picture structure. Signed-off-by: Christian König <[email protected]>
* st/vdpau: Use transfer_inline_write to upload ycbcr dataChristian König2012-02-211-18/+5
| | | | | | Uses less code and looks at least a bit cleaner than mapping manually. Signed-off-by: Christian König <[email protected]>
* st/vdpau: remove unnecessary tracing and adjust tracing levels a bitChristian König2012-02-217-64/+4
| | | | | | | | | Tracing function entry/exits is a bit pointless when VDPAU_TRACE=1 does the same thing. v2: use WARN instead of ERR for application problems Signed-off-by: Christian König <[email protected]>
* gallivm: Fix TGSI_OPCODE_ARR's translation.José Fonseca2012-02-213-2/+22
| | | | | | | | | | | | | Like TGSI_OPCODE_ARL, destination should be an integer. This fixes invalid LLVM IR on an internal state tracker (currently Mesa never emits this opcode). In the future consider making ADDR register also a integer-as-float array, like all other register kinds, or simply replace ADDR & ARR/ARL with integer temp and instructions. Reviewed-by: Dave Airlie <[email protected]>
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