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* r300g/compiler/tests: Fix segfaultTom Stellard2013-08-073-4/+4
| | | | CC: "9.2" <[email protected]>
* gallium-egl: Commit the rest of the native_wayland_drm_bufmgr_helper v2 patchKristian Høgsberg2013-08-073-7/+4
| | | | | | | | I missed Anders v2 on the list which fixed non-wayland compilation: http://lists.freedesktop.org/archives/mesa-dev/2013-July/042062.html Signed-off-by: Kristian Høgsberg <[email protected]>
* egl: Update to Wayland 1.2 server APIAnder Conselvan de Oliveira2013-08-0711-64/+90
| | | | | | | | | | Since Wayland 1.2, struct wl_buffer and a few functions are deprecated. References to wl_buffer are replaced with wl_resource and some getter functions and calls to deprecated functions are replaced with the proper new API. The latter changes are related to resource versioning. Signed-off-by: Ander Conselvan de Oliveira <[email protected]>
* gallium-egl: Don't add a listener for wl_drm twice in wayland platformAnder Conselvan de Oliveira2013-08-071-1/+0
| | | | | | | A listener is added just after the interface is bound, in registry_handle_global(). Signed-off-by: Ander Conselvan de Oliveira <[email protected]>
* gallium-egl: Simplify native_wayland_drm_bufmgr_helper interfaceAnder Conselvan de Oliveira2013-08-079-308/+276
| | | | | | | | | | | | | | | | | | | | | The helper provides a series of functions to easy the implementation of the WL_bind_wayland_display extension on different platforms. But even with the helpers there was still a bit of duplicated code between platforms, with the drm authentication being the only part that differs. This patch changes the bufmgr interface to provide a self contained object with a create function that takes a drm authentication callback as an argument. That way all the helper functions are made static and the "_helper" suffix was removed from the sources file name. This change also removes the mix of Wayland client and server code in the wayland drm platform source file. All the uses of libwayland-server are now contained in native_wayland_drm_bufmgr.c. Changes to the drm platform are only compile tested. Signed-off-by: Ander Conselvan de Oliveira <[email protected]>
* ilo: speed up 3DSTATE_VERTEX_BUFFERS emission a bitChia-I Wu2013-08-073-26/+12
| | | | Ignore vbuffer_mask which does not gain us anything.
* ilo: skip state emission when reducing sampler countChia-I Wu2013-08-071-19/+29
| | | | | When the number of sampler states bound is reduced, we are good to keep referencing the old SAMPLER_STATE array and skip emitting a new one.
* ilo: simplify setting of shader samplers and viewsChia-I Wu2013-08-071-44/+33
| | | | | Remove the special path that unbinds all samplers/views not in the range. Just make another call to unbind them.
* ilo: correctly check for stencil ref changeChia-I Wu2013-08-071-1/+1
| | | | I intended to do a memcmp(), not a memcpy()...
* draw: fix slot detectionZack Rusin2013-08-062-2/+1
| | | | | | | | | | | | Nowadays -1 for slots means that the semantic is not present, so we need to store it in a signed variables, otherwise <0 comparisons are pointless. Fixes http://bugzilla.eng.vmware.com/show_bug.cgi?id=67811 (at least with softpipe, edgeflags don't work wit llvmpipe) Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Fix build - Remove TargetOptions.RealignStack for llvm>=3.4Laurent Carlier2013-08-061-0/+2
| | | | | | | | | | Since llvm -3.4svn r187618, TargetOptions doesn't provide RealignStack, so only enable it with llvm<3.4 This option must now be specified using function attributes, see LLVM commit r187618 Reviewed-by: Tom Stellard <[email protected]>
* i965: Add #defines for the MI_LOAD_REGISTER_MEM command.Kenneth Graunke2013-08-061-0/+4
| | | | | | | | This command reads a value from memory and writes it to a register (the opposite of MI_STORE_REGISTER_MEM). It's only available on Gen7+. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Initialize the intel_context::bufmgr pointer earlier.Kenneth Graunke2013-08-061-2/+1
| | | | | | | | | | | | | | | | | This prevents a crash in a future patch. _mesa_initialize_context() creates a default transform feedback object by calling the NewTransformFeedbackObject() driver hook. Eventually, we'll want to subclass that and allocate a buffer object. This means passing brw->bufmgr to drm_intel_alloc_bo(), and crashing if it isn't initialized yet. The buffer manager is actually already initialized; we just hadn't copied the pointer from intel_screen to intel_context quite early enough. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Tidy preprocessor macros for SO_PRIM_STORAGE_NEEDED registers.Kenneth Graunke2013-08-061-5/+2
| | | | | | | | | | | | | | | Gen7+ supports four transform feedback streams. Using a function-like macro makes it easy to access them by stream number or loop over them. "GEN7_" prefixes are more common than "_IVB" suffixes, so use that. Gen6 only supports a single stream, so the single #define should be fine. However, SO_NUM_PRIM_STORAGE_NEEDED was a poor name. For one, the word "NUM" doesn't appear in the actual name of the register. It's also confusingly generic, as it doesn't exist on Gen7+. Add a "GEN6_" prefix for clarity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Tidy preprocessor macros for SO_NUM_PRIMS_WRITTEN registers.Kenneth Graunke2013-08-062-7/+4
| | | | | | | | | | | | | Gen7+ supports four transform feedback streams. Using a function-like macro makes it easy to access them by stream number or loop over them. "GEN7_" prefixes are more common than "_IVB" suffixes, so we use that. Gen6 only supports a single stream, so the single #define should be fine. However, SO_NUM_PRIMS_WRITTEN was confusingly generic, as it doesn't exist on Gen7+. Add a "GEN6_" prefix for clarity. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* nvc0: don't access array out of bounds on unexpected sample countChristoph Bumiller2013-08-061-2/+1
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* nv50: handle pure integer vertex attributesEmil Velikov2013-08-062-2/+14
| | | | | | | | And as a side effect fix a crash in the following piglit test: general/attribs GL3 Signed-off-by: Emil Velikov <[email protected]> Cc: "9.2 and 9.1" [email protected]
* nvc0: implement MP performance counters for nvc0:nvd9Samuel Pitoiset2013-08-062-93/+370
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* nvc0: implement compute support for nvc0Samuel Pitoiset2013-08-069-32/+706
| | | | Tested on nvc0, nvc1, nvcf and nvd9.
* nvc0: add more MP counters for nve4Samuel Pitoiset2013-08-063-14/+47
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* mesa: Generate a renderbuffer wrapper even if the texture has no imageIan Romanick2013-08-061-2/+3
| | | | | | | | | | This prevents a segfault in check_begin_texture_render when an FBO is rebound while in this state. This fixes the piglit test fbo-incomplete-invalid-texture. Signed-off-by: Ian Romanick <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Cc: "9.1 9.2" [email protected]
* mesa: Validate the layer selection of an array texture tooIan Romanick2013-08-061-4/+30
| | | | | | | | | | | | | | Previously only the slice of a 3D texture was validated in the FBO completeness check. This fixes the failure in the 'invalid layer of an array texture' subtest of piglit's fbo-incomplete test. v2: 1D_ARRAY textures have Depth == 1. Instead, compare against Height. v3: Handle CUBE_MAP_ARRAY textures too. Noticed by Marek. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "9.1 9.2" [email protected]
* mesa: Don't call driver RenderTexture for invalid zoffsetIan Romanick2013-08-061-0/+6
| | | | | | | | | | | | | | | This fixes the segfault in the 'invalid slice of 3D texture' and 'invalid layer of an array texture' subtests of piglit's fbo-incomplete test. The 'invalid layer of an array texture' subtest still fails. v2: Fix off-by-one comparison error noticed by Chris Forbes. Also, 1D_ARRAY textures have Depth == 1. Instead, compare against Height. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> [v1] Cc: "9.1 9.2" [email protected]
* mesa: Don't call driver RenderTexture for really broken texturesIan Romanick2013-08-061-2/+20
| | | | | | | | | This fixes the segfault in the '0x0 texture' subtest of piglit's fbo-incomplete test. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "9.1 9.2" [email protected]
* mesa: Remove stray debug printfs in attachment completeness codeIan Romanick2013-08-061-2/+0
| | | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: "9.1 9.2" [email protected]
* mesa: Treat glBindFramebuffer and glBindFramebufferEXT more correctlyIan Romanick2013-08-063-12/+20
| | | | | | | | | | | | | | | | | Allow user-generated names for glBindFramebufferEXT on desktop GL. Disallow its use altogether for core profiles. Names bound with glBindFramebuffer in desktop OpenGL are still (incorrectly) shared across the share group instead of being per-context. This gets us a bit closer to being strictly conformant. v2: Disallow glBindFramebufferEXT in 3.1 by not installing it in the dispatch table. Suggested by Jordan. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> [v1] Reviewed-by: Jordan Justen <[email protected]> [v1] Cc: [email protected]
* mesa: Treat glBindRenderbuffer and glBindRenderbufferEXT correctlyIan Romanick2013-08-063-8/+19
| | | | | | | | | | | | | Allow user-generated names for glBindRenderbufferEXT on desktop GL. Disallow its use altogether for core profiles. v2: Disallow glBindRenderbufferEXT in 3.1 by not installing it in the dispatch table. Suggested by Jordan. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> [v1] Reviewed-by: Jordan Justen <[email protected]> [v1] Cc: [email protected]
* radeonsi: Number of SGPRs retrieved from LLVM already includes VCCMichel Dänzer2013-08-061-8/+8
| | | | | | | | Fixes spurious 'Assertion `num_sgprs <= 104' failed.' with shaders using all 104 SGPRs. Cc: [email protected] Reviewed-by: Christian König <[email protected]>
* i965: Don't allocate curbe buffers on Gen6+.Kenneth Graunke2013-08-061-2/+4
| | | | | | | These are only used on Gen4-5. Why waste the 8kB of space? Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* llvmpipe: Do not need to free anything if there is no geometry shader.Vinson Lee2013-08-051-2/+5
| | | | | | | | | | If gs is null, then freeing state->shader.tokens would result in a null dereference. Fixes "Dereference after null check" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* nvc0: Initialize ptr for unexpected sample_count on release builds.Vinson Lee2013-08-051-0/+1
| | | | | | | Fixes "Uninitialized pointer read" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* draw: Change slot from unsigned to int.Vinson Lee2013-08-051-1/+1
| | | | | | | | | unfilled_stage::face_slot is of type int. Fixes "Unsigned compared against 0" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* postprocess: Check ppq is null before calling pp_free_bos.Vinson Lee2013-08-051-1/+3
| | | | | | | | | pp_free_bos dereferences ppq without a null check. Fixes "Dereference before null check" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* draw: add back separate input assemblerZack Rusin2013-08-036-4/+351
| | | | | | | | | | | the issue is that stream output is run before the pipeline, which means that unless we decompose the primitives before the so then things crash. we could convert the entire stream output code into a pipeline stage but it will take a bit, so for now fix the crashes by simply re-adding the old input assembler which is run before the SO. Signed-off-by: Zack Rusin <[email protected]>
* draw: implement proper primitive assembler as a pipeline stageZack Rusin2013-08-0312-352/+280
| | | | | | | | | | | | | we used to have a face primitive assembler that we ran after if the gs was missing but we had adjacency primitives in the pipeline, lets convert it to a pipeline stage, which allows us to use it to inject outputs (primitive id) into the vertices. it's also a lot cleaner because the decomposition is already handled for us. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* draw: fix front face injectionZack Rusin2013-08-031-9/+15
| | | | | | | | | | | | | Inject front face only if the fragment shader uses it and propagate through all channels because otherwise we'll need to figure out the exact swizzle that the fs expects and it's just simpler to make sure all the components within the front face register are correctly set. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* tgsi: remove unneeded File == TGSI_FILE_INPUT testBrian Paul2013-08-051-1/+0
| | | | We're already in an "if (File == TGSI_FILE_INPUT)" block at that point.
* tgsi: clean up tgsi_scan_shader() functionBrian Paul2013-08-051-41/+42
| | | | | | | | | Replace "fulldecl->Semantic.Name/Index" with semName/semIndex. Simplify if/else logic for TGSI_FILE_OUTPUT code. Remove old comment. Fix indentation. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix frontface behavior againZack Rusin2013-08-021-3/+11
| | | | | | | Lets make sure the frontface is 1 for front and -1 for back. Discussed with Roland and Jose. Signed-off-by: Zack Rusin <[email protected]>
* r600g/sb: Dump correct value for CND.Vinson Lee2013-08-041-1/+1
| | | | | | | Fixes "Copy-paste error" reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Vadim Girlin <[email protected]>
* intel_fbo: remove unused intel_renderbuffer hiz functionsJordan Justen2013-08-042-26/+0
| | | | | | | | | We are now using functions that operate on the renderbuffer attachment to handle layered rendering. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965 clear/draw: set renderbuffer attachment as needing depth resolveJordan Justen2013-08-042-2/+4
| | | | | | | | | | | Previously we would mark a renderbuffer as needing a depth resolve. But, to support layered rendering, we need to look at the attachment instead, since the attachment knows if layered rendering is being used. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: add intel_renderbuffer_att_set_needs_depth_resolveJordan Justen2013-08-042-0/+18
| | | | | | | | | | This function is needed to support layered rendering. With layered rendering, the attachment stores the state of whether layered rendering is being used. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: add intel_miptree_set_all_slices_need_depth_resolveJordan Justen2013-08-042-0/+16
| | | | | | | | | This function marks all slices of a renderbuffer at a particular level as needing a depth resolve. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965 gen7: don't set FORCE_ZERO_RTAINDEX for layered renderingJordan Justen2013-08-041-1/+1
| | | | | | | | | When layered rendering is being used, we should not set FORCE_ZERO_RTAINDEX in the clip state to allow render target array values other than zero to be used. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* hsw hiz: Remove x/y offset restriction for hizJordan Justen2013-08-041-24/+0
| | | | | | | | | This restriction was related to programming the offset fields of the depth buffer packet. We are now setting these offsets to 0 now, so this restriction should no longer be required. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* gen7 depth surface: program 3DSTATE_DEPTH_BUFFER to top of surfaceJordan Justen2013-08-044-66/+45
| | | | | | | | | | | | | | | | | | | | | Previously we would always find the 2D sub-surface of interest, and then program the surface to this location. Now we always program the 3DSTATE_DEPTH_BUFFER at the start of the surface. To select the lod/slice, we utilize the lod & minimum array element fields. As part of this change, we must revert 1f112ccf: Revert "i965/gen7: Align all depth miplevels to 8 in the X direction." We also must disable brw_workaround_depthstencil_alignment for gen >= 7. Now the hardware will handle alignment when rendering to additional slices/LODs. v2: * Merge with recent MOCS changes Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* gen7 fbo: make unmatched depth/stencil configs return unsupportedJordan Justen2013-08-041-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | For gen >= 7, we will use the lod/minimum-array-element fields to support layered rendering. This means that we must restrict the depth & stencil attachments to match in various more retrictive ways. (Now the width, height, depth, LOD and layer must match) The reason width, height, and depth must match is that the hardware has a single set of width, height, and depth settings (in 3DSTATE_DEPTH_BUFFER) that affect both the depth and stencil buffers. Since these controls determine the miptree layout, they need to be set correctly in order for lod and minimum-array-element to work properly. So the only way rendering can work is if the width, height, and depth match. In the future, if this restriction proves to be a problem (say because some crucial client application relies on rendering to different levels/layers of stencil and depth buffers), then we can always work around the restriction by copying depth and/or stencil data to a temporary buffer prior to rendering (much in the same way that brw_workaround_depthstencil_alignment() does today for gen < 7), but hopefully that won't be necessary. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* hsw hiz: Add new size restrictions for miplevels > 0Jordan Justen2013-08-041-3/+13
| | | | | | | | | | | When performing hiz ops, we must ensure that the region sizes have an 8 aligned width and 4 aligned height. We can tweak the size for blorp hiz operations at LOD 0, but for the others we can't. Therefore, we disable hiz for these miplevels if they don't meet the size alignment requirements. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* gen7 blorp depth: calculate base surface width/heightJordan Justen2013-08-041-0/+13
| | | | | | | This will be used in 3DSTATE_DEPTH_BUFFER in a later patch. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Paul Berry <[email protected]>
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