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* i965: add performance query support on CNLLionel Landwerlin2018-03-224-1/+10415
| | | | | | | v2: Add brw_oa_cnl.xml to EXTRA_DIST (Emil) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965: perf: add support for new equation operatorsLionel Landwerlin2018-03-221-0/+15
| | | | | | | | Some equations of the CNL metrics started to use operators we haven't defined yet, just add those. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: perf: query topologyLionel Landwerlin2018-03-222-71/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. We introduce a new uAPI in the kernel driver to report exactly what part of the GPU are fused and require this to be available on Gen10+. Prior generations can continue to rely on GETPARAM on older kernels. This patch is quite a lot of code because we have to support lots of different kernel versions, ranging from not providing any information (for Haswell on 4.13 through 4.17), to being able to query through GETPARAM (for gen8/9 on 4.13 through 4.17), to finally requiring 4.17 for Gen10+. This change stores topology information in a unified way on brw_context.topology from the various kernel APIs. And then generates the appropriate values for the equations from that unified topology. v2: Move slice/subslice masks fields to gen_device_info (Rafael) v3: Add a gen_device_info_subslice_available() helper (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: add helper functions to fill fusing masks valuesLionel Landwerlin2018-03-222-1/+140
| | | | | | | | | | | | | | | | | | | | | | There are a couple of ways we can get the fusing information from the kernel : - Through DRM_I915_GETPARAM with the SLICE_MASK/SUBSLICE_MASK parameters - Through the new DRM_IOCTL_I915_QUERY by requesting the DRM_I915_QUERY_TOPOLOGY_INFO The second method is more accurate and also gives us the EUs fusing masks. It's also a requirement for CNL as this platform has asymetric subslices and the first method SUBSLICE_MASK value is assumed uniform across slices. v2: Change gen_device_info_update_from_masks() to generate topology and call into gen_device_info_update_from_topology (Lionel/Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: meson: include drm uapiLionel Landwerlin2018-03-221-1/+1
| | | | | | | Already available with the autotools build. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: store slice/subslice/eu masksLionel Landwerlin2018-03-222-1/+91
| | | | | | | | | | | We want to store values coming from the kernel but as a first step, we can generate mask values out the numbers already stored in the gen_device_info masks. v2: Add a helper to set EU masks (Lionel/Ken) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: devinfo: store number of EUs per subsliceLionel Landwerlin2018-03-222-2/+38
| | | | | | | | | | | This will be reused to store values reported by the kernel. The main use case will be for use as the input values of the metric sets equations for the INTEL_performance_queries extension. By storing this information in the gen_device_info we make this non GL specific so this can be reused by Vulkan if we ever have an equivalent extension. Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/perf: fix config registration when uploading to kernelLionel Landwerlin2018-03-221-1/+1
| | | | | | | | | | | | | | When registring configurations to the kernel for the first time, we run into an issue where the id number is not properly set (we're using the wrong variable). As a result when trying to use that id later on, we get an error. This issue manifest itself the first time you use frameretrace after reboot, subsequent runs are fine. Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations") Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* gallium/winsys/kms: Add support for multi-planesLepton Wu2018-03-221-40/+112
| | | | | | | | | | | | | | | | | | | | | | | Add a new struct kms_sw_plane which delegate a plane and use it in place of sw_displaytarget. Multiple planes share same underlying kms_sw_displaytarget. v2: - add more check for plane size (Tomasz) v3: - split from larger patch (Emil) v4: - no change from v3 v5: - remove mapped field (Tomasz) v6: - remove change-id in commit message (Tomasz) v7: - add revision history in commit message (Emil) Reviewed-by: Tomasz Figa <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Lepton Wu <[email protected]>
* gallium/winsys/kms: Fix possible leak in map/unmap.Lepton Wu2018-03-221-7/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If user calls map twice for kms_sw_displaytarget, the first mapped buffer could get leaked. Instead of calling mmap every time, just reuse previous mapping. Since user could map same displaytarget with different flags, we have to keep two different pointers, one for rw mapping and one for ro mapping. Also introduce reference count for mapped buffer so we can unmap them at right time. v2: - avoid duplicated mapping and leaked mapping (Tomasz) v3: - split from larger patch (Emil) v4: - remove munmap from dt_destory (Emil) v5: - introduce reference count for mapping (Tomasz) - add back munmap in dt_destory v6: - remove change-id in commit message (Tomasz) v7: - remove munmap from dt_destory again (Emil) - add revision history in commit message (Emil) Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Tomasz Figa <[email protected]> Signed-off-by: Lepton Wu <[email protected]>
* broadcom/vc4: add path to nir_builder.hJuan A. Suarez Romero2018-03-221-1/+1
| | | | | | | | As the other VC4 files do. Otherwise, it won't find nir_builder.h v2: add path in source code rather changing autotools (Emil) Reviewed-by: Emil Velikov <[email protected]>
* autotools: add tegra header filesJuan A. Suarez Romero2018-03-221-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* swr/rast: autotools: add events_private.proto in dist tarball.Juan A. Suarez Romero2018-03-221-0/+1
| | | | Reviewed-by: Emil Velikov <[email protected]>
* radv: autotools: add radv_extensions.h in the generated VULKAN listJuan A. Suarez Romero2018-03-221-1/+2
| | | | Reviewed-by: Emil Velikov <[email protected]>
* anv/radv: autotools: include vulkan_*.h headersJuan A. Suarez Romero2018-03-222-0/+8
| | | | Reviewed-by: Emil Velikov <[email protected]>
* nir: autotools, meson: add GLSL.ext.AMD.h in the files listJuan A. Suarez Romero2018-03-222-0/+2
| | | | Reviewed-by: Emil Velikov <[email protected]>
* intel/compiler: Readd ICL to test_eu_validate.cppMatt Turner2018-03-221-0/+1
| | | | Now that the PCI IDs are upstream, this can be readded.
* intel/compiler: Skip 64-bit type tests when types not availableMatt Turner2018-03-221-0/+19
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Disable fast color clear on iclAnuj Phogat2018-03-221-0/+5
| | | | | | | | | Disabling fast color clear makes fbo-clearmipmap test render correct texture in base miplevel. Fast color clear is anyways disabled for non-base miplevels. Acked-by: Matt Turner <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* intel/compiler/icl: Clear "null render target" bit in extended message ↵Jason Ekstrand2018-03-222-0/+6
| | | | | | | | | descriptor Otherwise all our render target writes go no where. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/compiler/icl: Update the assert in brw_stage_has_packed_dispatch()Anuj Phogat2018-03-221-1/+1
| | | | | | | | Rafael ran piglit with the test code enabled and saw no additional GPU hangs. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common/icl: Disable hiz surface samplingAnuj Phogat2018-03-221-0/+1
| | | | | | | | On gen11+ AUX_HIZ is not a supported value for surfaces being sampled by the 3D sampler. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel/common/icl: Add L3 configAnuj Phogat2018-03-221-0/+18
| | | | | | ICL uses the same L3 configs as CNL, just leaving the SLM configs out. Reviewed-by: Kenneth Graunke <[email protected]>
* intel/tools/aubinator: Drop platform list from print_help()Matt Turner2018-03-221-1/+1
| | | | | | | | We all know the platform names, and I don't want to update this list continually. Reviewed-by: Rafael Antognolli <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* egl/wayland: Make swrast display_sync the correct queueDerek Foreman2018-03-221-1/+1
| | | | | | | | | | | | | | commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface queues, but the display_sync for swrast_commit_backbuffer remained on the old queue. This is likely to break when dispatching the correct queue at the top of function (which can't dispatch the sync callback we're waiting for). The easiest known reproduction case is running weston-subsurfaces under weston --use-pixman Signed-off-by: Derek Foreman <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* radv: remove unused radv_pipeline::needs_data_cache variableSamuel Pitoiset2018-03-221-1/+0
| | | | Signed-off-by: Samuel Pitoiset <[email protected]>
* vbo: Remove now duplicate _DrawVAO notification.Mathias Fröhlich2018-03-221-5/+0
| | | | | | | | | | | The DriverFlags.NewArray bit is already set to NewDriverState in _mesa_set_draw_vao since we have actually just above changed the VAOs content. So this can be removed. The _vbo_update_inputs is called by the vbo...recalculate_inputs being set through the same mechanism as described above. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove now duplicate _vbo_update_inputs from dlist draw.Mathias Fröhlich2018-03-221-3/+0
| | | | | | | | | | | At the current state, _vbo_update_inputs is called from the draw callback if vbo...recalculate_inputs is set. But that is now set of the _DrawVAO or its content or the vertex program mode is changed. So remove _vbo_update_inputs from the direct dlist draw path. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove redundant set of DriverFlags.NewArray in vbo_bind_arrays.Mathias Fröhlich2018-03-221-1/+0
| | | | | | | | | Now that setting vbo...recalculate_inputs also sets the DriverFlags.NewArray bits into the NewDriverState setting that from vbo_bind_arrays is redundant. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Remove vbo...recalculate_inputs from vbo_exec_invalidate_state.Mathias Fröhlich2018-03-221-8/+0
| | | | | | | | This flag is now set when the actual Array._DrawVAO changes. So setting this flag is redundant here. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: A change of gl_vertex_processing_mode needs an array update.Mathias Fröhlich2018-03-221-3/+17
| | | | | | | | | Since arrays also handle the mapping of current values into the disabled array slots, we need to tell the array update code that this mapping has changed. Also mark only dirty if it has changed. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Set DriverFlags.NewArray together with vbo...recalculate_inputs.Mathias Fröhlich2018-03-223-3/+32
| | | | | | | | | | Both mean something very similar and are set at the same time now. For that vbo module to be set from core mesa, implement a public vbo module method to set that flag. In the longer term the flag should vanish in favor of a driver flag of the appropriate driver. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Update VAO internal state when setting the _DrawVAO.Mathias Fröhlich2018-03-223-8/+13
| | | | | | | | | | | | Update the VAO internal state on Array._DrawVAO instead of Array.VAO. Also the VAO internal state update gets triggered now by a change of Array._DrawVAO instead of the _NEW_ARRAY state flag. Also no driver looks at any VAO's NewArrays value from within the Driver.UpdateState callback. So it should be safe to move this update into the _mesa_set_draw_vao method. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* vbo: Move vbo_bind_arrays into a dd_driver_functions draw callback.Mathias Fröhlich2018-03-224-46/+27
| | | | | | | | | | | | Factor out that common call into the almost single place. Remove the _mesa_set_drawing_arrays call from vbo_{exec,save}_draw code paths as the function is now called through vbo_bind_arrays. Prepare updating the list of struct gl_vertex_array entries via calling _vbo_update_inputs for being pushed into those drivers that finally work on that long list of gl_vertex_array pointers. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* mesa: Move vbo draw functions into dd_function_table.Mathias Fröhlich2018-03-229-48/+162
| | | | | | | | Move vbo draw functions into struct dd_function_table. For now just wrap the underlying vbo functions. Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]>
* clover/llvm: Fix build against LLVM/Clang 4.0Aaron Watry2018-03-212-1/+3
| | | | | | | | The opencl 1.0 langstandard was renamed in 5.0+ v2: Move preprocessor check into compat.hpp Reviewed-by: Francisco Jerez <[email protected]>
* ac/nir_to_llvm: add frexp supportTimothy Arceri2018-03-221-0/+11
| | | | | | | | | | | | | | Fixes CTS tests: KHR-GL40.gpu_shader_fp64.builtin.frexp_double KHR-GL40.gpu_shader_fp64.builtin.frexp_dvec2 KHR-GL40.gpu_shader_fp64.builtin.frexp_dvec3 KHR-GL40.gpu_shader_fp64.builtin.frexp_dvec4 And piglit test: tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4.shader_test Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: add frexp_exp and frexp_sig opcodesTimothy Arceri2018-03-222-0/+5
| | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* anv/pipeline: don't pass constant view index in multiviewCaio Marcelo de Oliveira Filho2018-03-211-6/+11
| | | | | | | | | | | If view mask has only one bit set, view index is effectively a constant, so doesn't need to be passed to the next stages, just always set it. Part of this was in the original patch that added anv_nir_lower_multiview.c but disabled. Reviewed-by: Jason Ekstrand <[email protected]>
* anv/pipeline: use less instructions for multiviewCaio Marcelo de Oliveira Filho2018-03-211-1/+1
| | | | | | | | | | | | | | | The view_index is encoded in the remainder of dividing instance id by the number of views in the view mask (n). In the general case (handled by the else clause), there is a need to map from 0..n-1 into the number of the view being masked. For that a map is encoded. In the case only the first n bits in the mask are set, the mapping is trivial, 0..n-1 already represent what view is being referred to. That case was in the original patch that added anv_nir_lower_multiview.c but disabled. Reviewed-by: Jason Ekstrand <[email protected]>
* broadcom/vc5: Fix up the NIR types of FS outputs generated by NIR-to-TGSI.Eric Anholt2018-03-214-0/+54
| | | | | | | | | | Unfortunately TGSI doesn't record the type of the FS output like GLSL does, but VC5's TLB writes depend on the output's base type. Just record the type in the key at variant compile time when we've got a TGSI input and then fix it up. Fixes KHR-GLES3.packed_pixels.pbo_rectangle.rgba32i/ui and apparently a GPU hang that breaks most tests that come after it.
* spirv: Add a 64-bit implementation of FrexpNeil Roberts2018-03-211-4/+56
| | | | | | | | | | The implementation is inspired by lower_instructions_visitor::dfrexp_sig_to_arith. This has been tested against the arb_gpu_shader_fp64/fs-frexp-dvec4 test using the ARB_gl_spirv branch. Reviewed-by: Jason Ekstrand <[email protected]>
* aubinator_error_decode: Compare only the class_name of the ring.Rafael Antognolli2018-03-211-1/+1
| | | | | | | | | | | ring_name is "<class_name> + <instance_id>" (e.g. rcs0). So we need to first compare the class name only, then get the instance id. Without this, INSTDONE is not being decoded. Signed-off-by: Rafael Antognolli <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]>
* nir: Migrate nir_dce to instr worklistThomas Helland2018-03-211-35/+18
| | | | | | | | | Shader-db runtime change avarage of five runs: Before 125,77 seconds (+/- 0,09%) After 124,48 seconds (+/- 0,07%) Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de> Reviewed-by: Eric Anholt <eric at anholt.net>
* nir: Initial implementation of a nir_instr_worklistThomas Helland2018-03-211-0/+67
| | | | | | | | | | Make a simple worklist by basically just wrapping u_vector. This is intended used in nir_opt_dce to reduce the number of calls to ralloc, as we are currenlty spamming ralloc quite bad. It should also give better cache locality and much lower memory usage. Tested-by: Dieter Nützel <Dieter at nuetzel-hh.de> Reviewed-by: Eric Anholt <eric at anholt.net>
* intel/tools: aubinator: Catch gen11 "enhanced execlist" submissionScott D Phillips2018-03-211-6/+20
| | | | | | | | | Different registers are used for execlist submission in gen11, so also watch those. This code only watches element zero of the submit queue, which is all aubdump currently writes. Tested-by: Rafael Antognolli <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]>
* radeonsi: fix a snprintf warning on gcc 7.3.0Marek Olšák2018-03-211-1/+1
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* radeonsi/gfx9: print the swizzle mode for testdmaMarek Olšák2018-03-211-2/+16
| | | | Tested-by: Dieter Nützel <[email protected]>
* ac/surface: compute tile swizzle for GFX9Marek Olšák2018-03-214-3/+91
| | | | Tested-by: Dieter Nützel <[email protected]>
* broadcom/vc5: Don't skip job submit just because everything is scissored.Eric Anholt2018-03-212-10/+7
| | | | | | | | The coordinate shaders may now have side effects in the form of transform feedback. Part of fixing GTF-GLES3.gtf.GL3Tests.transform_feedback.transform_feedback_misc
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