summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Collapse)AuthorAgeFilesLines
* freedreno: add -Wno-packed-bitfield-compat for meson buildEric Engestrom2017-12-041-2/+12
| | | | | | | | | | | Otherwise huge amount of spam from instr-a2xx.h.. gcc has no way to know that freedreno was never built with such an old gcc version to care about the bugs in old gcc ;-) Reported-by: Rob Clark <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> [added commit message] Signed-off-by: Rob Clark <[email protected]>
* glsl: don't run intrastage array validation when the interface type is not ↵Samuel Iglesias Gonsálvez2017-12-041-1/+1
| | | | | | | | | | | | | | | | | an array We validate that the interface block array type's definition matches. However, previously, the function could be called if an non-array interface block has different type definitions -for example, when the precision qualifier differs in a GLSL ES shader, we would create two different types-, and it would return invalid as both definitions are non-arrays. We fix this by specifying that at least one definition should be an array to call the validation. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl/es: precision qualifier doesn't need to match in UBOsSamuel Iglesias Gonsálvez2017-12-041-1/+1
| | | | | | | | | They might mismatch due to the two shaders using different GLSL versions, and that's ok in desktop GL. In ES, precision qualifiers don't need to match. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* nvc0/ir: Properly lower 64-bit shifts when the shift value is >32Pierre Moreau2017-12-041-1/+1
| | | | | | | | | | | | | | | | | | | | Fixes: 61d7676df77 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30" Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current set-up: uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901 uniform uint64_t uval 0x1400000085010203 uniform int shl 36 uniform int shr 36 uniform int64_t iexpected_shl 0x09ac901000000000 uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010 uniform uint64_t uexpected_shl 0x5010203000000000 uniform uint64_t uexpected_shr 0x0000000001400000 draw rect ortho 12 0 4 4 Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* glsl: Match order of gl_LightSourceParameters elements.Fabian Bieler2017-12-031-2/+2
| | | | | | | | | spotExponent and spotCosCutoff were swapped in the gl_builtin_uniform_element struct. Now the order matches across gl_builtin_uniform_element, glsl_struct_field and the spec. Reviewed-by: Brian Paul <[email protected]>
* glsl: Fix gl_NormalScale.Fabian Bieler2017-12-033-2/+6
| | | | | | | | | | | | | | | | GLSL shaders can access the normal scale factor with the built-in gl_NormalScale. Mesa's modelspace lighting optimization uses a different normal scale factor than defined in the spec. We have to take care not to use this factor for gl_NormalScale. Mesa already defines two seperate states: state.normalScale and state.internal.normalScale. The first is used by the glsl compiler while the later is used by the fixed function T&L pipeline. Previously the only difference was some component swizzling. With this commit state.normalScale always uses the normal scale factor for eyespace lighting. Reviewed-by: Brian Paul <[email protected]>
* st/glsl_to_nir/radeonsi: enable gs support for nir backendTimothy Arceri2017-12-043-29/+47
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add si_nir_load_input_gs() to the abiTimothy Arceri2017-12-045-14/+64
| | | | | | | V2: make use of driver_location and don't expose NIR to the ABI. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: move build_varying_gather_values() to ac_llvm_build.h and exposeTimothy Arceri2017-12-043-28/+32
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* ac: add basic nir -> llvm type helperTimothy Arceri2017-12-041-0/+22
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: create si_llvm_load_input_gs()Timothy Arceri2017-12-042-23/+44
| | | | | | | | | | This creates a common function that can be shared by the tgsi and nir backends. v2: use LLVMBuildBitCast() directly Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: pass llvm type to lds_load()Timothy Arceri2017-12-041-13/+13
| | | | | | | v2: use LLVMBuildBitCast() directly Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add llvm_type_is_64bit() helperTimothy Arceri2017-12-041-0/+9
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()Timothy Arceri2017-12-043-12/+18
| | | | | | | v2: use LLVMBuildBitCast() directly Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add nir support for gs epilogueTimothy Arceri2017-12-041-4/+21
| | | | | | | v2: add emit_gs_epilogue() helper function to reduce duplication. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add nir support for es epilogueTimothy Arceri2017-12-041-16/+13
| | | | | | | v2: make use of existing si_tgsi_emit_epilogue() Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: add nir support for ls epilogueTimothy Arceri2017-12-041-15/+14
| | | | | | | v2: make use of existing si_tgsi_emit_epilogue() Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir: add gs support to st_nir_assign_var_locations()Timothy Arceri2017-12-041-6/+17
| | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir: use nir_lower_io_arrays_to_elements() to lower arraysTimothy Arceri2017-12-041-1/+1
| | | | | | | | This pass is more fully featured, it supports geom and tess shaders. It also supports interpolation intrinsics. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: allow builin arrays to be loweredTimothy Arceri2017-12-041-7/+10
| | | | | | | Galliums nir drivers expect this to be done. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: add array lowering function that assumes there are no indirectsTimothy Arceri2017-12-042-1/+44
| | | | | | | | | | The gallium glsl->nir pass currently lowers away all indirects on both inputs and outputs. This fuction allows us to lower vs inputs and fs outputs and also lower things one stage at a time as we don't need to worry about indirects on the other side of the shaders interface. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radv: enable nir varying array splittingTimothy Arceri2017-12-041-0/+3
| | | | Acked-by: Dave Airlie <[email protected]>
* st/glsl_to_nir: enable NIR link time optsTimothy Arceri2017-12-042-7/+105
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/nir: add support for packed inputsTimothy Arceri2017-12-041-21/+25
| | | | | | | | | Because NIR can create non vec4 variables when implementing component packing we need to make sure not to reprocess the same slot again. Also we can drop the fs_attr_idx counter and just use driver_location. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: move some calls out of st_glsl_to_nir_post_opts()Timothy Arceri2017-12-041-30/+37
| | | | | | | NIR component packing will be inserted between these calls and the calling of st_glsl_to_nir_post_opts(). Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: call some lowering passes earlierTimothy Arceri2017-12-041-8/+12
| | | | | | This is required so that we can enbale NIR linking optimisations. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: add basic NIR opt loop helperTimothy Arceri2017-12-041-0/+31
| | | | | | | | We need to be able to do these NIR opts in the state tracker rather than the driver in order for the NIR linking opts to be useful. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: make st_glsl_to_nir() staticTimothy Arceri2017-12-042-55/+51
| | | | | | Here we also move the extern C functions to the bottom of the file. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: split the st_glsl_to_nir() function in twoTimothy Arceri2017-12-041-22/+34
| | | | | | | | We want to be able to generate NIR then apply NIR optimisations. Once the optimisations are done we can then apply the new post opt function which assigns uniforms etc based on the optimised IR. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: create set_st_program() helperTimothy Arceri2017-12-041-34/+40
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl: move nir linking loop to new function st_link_nir()Timothy Arceri2017-12-043-17/+41
| | | | | | | This will allow us to refactor linking and include some nir link time optimisations. Reviewed-by: Nicolai Hähnle <[email protected]>
* nir: fix support for scalar arrays in nir_lower_io_types()Timothy Arceri2017-12-041-7/+3
| | | | | | | This was just recreating the same vector type we alreay had and hitting an assert for scalars. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: add st_nir_assign_var_locations() helperTimothy Arceri2017-12-041-9/+34
| | | | | | This avoids packed varyings being assigned different driver locations. Reviewed-by: Nicolai Hähnle <[email protected]>
* radv: enable nir component packingTimothy Arceri2017-12-041-0/+6
| | | | | | | | SaschaWillems Vulkan demo tessellation: ~4000fps -> ~4600fps Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: add varying component packing helpersTimothy Arceri2017-12-042-0/+332
| | | | | | | | | | | | v2: update shader info input/output masks when pack components v3: make sure interpolation loc matches, this is required for the radeonsi NIR backend. v4: 33dca36f4f28 fixed nir_gather_info to update outputs_read correct, make sure we also adjust this correctly when packing components. Reviewed-by: Bas Nieuwenhuizen <[email protected]> (v1) Reviewed-by: Nicolai Hähnle <[email protected]> (v3)
* nir: add varying array splitting passTimothy Arceri2017-12-044-0/+386
| | | | | | | | | | | | | V2: - fix matrix support, non-array matrices were being skipped in v1 v3: - handle lowering of tcs output loads correctly - correctly mark indirect locations for either in or out not both when processing a stage. - use nir_src_copy() when lowering stores. Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno/ir3: relax barriersRob Clark2017-12-031-2/+2
| | | | | | Instructions with no barrier_class can move wrt. an EVERYTHING barrier. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: all mem instructions have WAR hazzardRob Clark2017-12-031-1/+1
| | | | | | | | It isn't just load instructions that have write-after-read hazzard. Fixes stk gaussian blur compute shaders. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add debug option to force emulated indirectRob Clark2017-12-033-0/+12
| | | | | | Useful mostly for debugging indirect draw. Signed-off-by: Rob Clark <[email protected]>
* freedreno: also mark draw-indirect buffer as readRob Clark2017-12-031-0/+7
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: small cleanupsRob Clark2017-12-031-17/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: avoid unneccessary batch flushRob Clark2017-12-031-0/+2
| | | | | | | | | In some cases we can end up trying to add a write dependency on ourself, which shouldn't trigger a flush. Avoids an extra couple flushes per from in stk. Signed-off-by: Rob Clark <[email protected]>
* freedreno: avoid mem2gmem for invalidated buffersRob Clark2017-12-033-2/+17
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: deferred flush supportRob Clark2017-12-035-4/+32
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: rework fence trackingRob Clark2017-12-0312-61/+109
| | | | | | | | | ctx->last_fence isn't such a terribly clever idea, if batches can be flushed out of order. Instead, each batch now holds a fence, which is created before the batch is flushed (useful for next patch), that later gets populated after the batch is actually flushed. Signed-off-by: Rob Clark <[email protected]>
* freedreno: proper locking for iterating dependent batchesRob Clark2017-12-032-8/+20
| | | | | | | | | In transfer_map(), when we need to flush batches that read from a resource, we should be holding screen->lock to guard against race conditions. Somehow deferred flush seems to make this existing race more obvious. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: correct max_indicies for indirect drawsRob Clark2017-12-031-1/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* spirv: Convert the supported_extensions struct to spirv_optionsJason Ekstrand2017-12-025-37/+44
| | | | | | | | This is a bit more general and lets us pass additional options into the spirv_to_nir pass beyond what capabilities we support. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* spirv: Only emit functions which are actually usedJason Ekstrand2017-12-023-8/+26
| | | | | | | | | | Instead of emitting absolutely everything, just emit the few functions that are actually referenced in some way by the entrypoint. This should save us quite a bit of time when handed large shader modules containing many entrypoints. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
* spirv: Drop the impl field from vtn_builderJason Ekstrand2017-12-024-8/+6
| | | | | | | We have a nir_builder and it has an impl field. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Kristian H. Kristensen <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 04:58:11 +0000