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* i965/blorp: unit test compiling simple gen6 zero-src sampledTopi Pohjolainen2013-12-271-0/+51
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling gen6 msaa-8 cms alpha blendTopi Pohjolainen2013-12-271-0/+57
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling bilinear filteredTopi Pohjolainen2013-12-271-0/+49
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling simple zero-src sampledTopi Pohjolainen2013-12-271-0/+56
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling unaligned msaa-8Topi Pohjolainen2013-12-271-0/+135
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling msaa-8 cms alpha blendTopi Pohjolainen2013-12-271-0/+145
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling msaa-4 ums to cmsTopi Pohjolainen2013-12-271-0/+59
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling msaa-8 cms to cmsTopi Pohjolainen2013-12-271-0/+62
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling msaa-8 ums to cmsTopi Pohjolainen2013-12-271-0/+61
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: unit test compiling blend and scaledTopi Pohjolainen2013-12-273-1/+339
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: allow unit tests to compile and dump assemblyTopi Pohjolainen2013-12-271-3/+16
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: dump the disassembly to the given fileTopi Pohjolainen2013-12-271-10/+10
| | | | | | | | instead of ignoring the argument and always dumping to standard output. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: allow fs-generator use without gl_fragment_programTopi Pohjolainen2013-12-271-3/+6
| | | | | | | Prepares the generator to accept hand-crafted blorp programs. Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: generate fs programs also without any 8-width instructionsTopi Pohjolainen2013-12-271-2/+6
| | | | | Signed-off-by: Topi Pohjolainen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* freedreno/a3xx: fix blend state corruption issueRob Clark2013-12-268-33/+66
| | | | | | | | | | | | | | | | | | | | | | Using RMW on banked context registers is not safe. The value read could be the wrong one. So if there has been a DRAW_IDX launched, the RMW must be preceded by a WAIT_FOR_IDLE to ensure the read part of RMW sees the correct value. To avoid unnecessary WFI's, keep track if there is a need for WFI, and only emit one if needed. Furthermore, keep track if we even need to update the register in the first place. And to cut down on the amount of RMW to avoid excessive WFI's, at the tiling/GMEM level we can always overwrite RB_RENDER_CONTROL, as the state at beginning of draw/clear cmds (which we IB to) is always undefined. In the draw/clear commands, we always still use RMW (with WFI if needed), but only if the register value actually changes. (At points where the current value cannot be known, the saved value is reset to ~0, which includes bits outside of RBRC_DRAW_STATE, so there never is chance for confusion.) Signed-off-by: Rob Clark <[email protected]>
* freedreno: prepare for hw binningRob Clark2013-12-269-142/+159
| | | | | | | | | | | | Actually assign VSC_PIPE's properly, which will be needed for tiling. And introduce fd_tile for per-tile state (including the assignment of tile to VSC_PIPE). This gives us the proper pipe setup that we'll need for hw binning pass, and also cleans things up a bit by not having to pass so many parameters around. And will also make it easier to introduce different tiling patterns (since we may no longer render tiles in a simple left-to-right top-to-bottom pattern). Signed-off-by: Rob Clark <[email protected]>
* freedreno: resync generated headersRob Clark2013-12-266-76/+131
| | | | Signed-off-by: Rob Clark <[email protected]>
* r600/pipe: Stop leaking context->start_compute_cs_cmd.buf on EG/CMAaron Watry2013-12-231-0/+2
| | | | | | | | Found while tracking down memory leaks in VDPAU playback Reviewed-by: Tom Stellard <[email protected]> CC: "10.0" <[email protected]>
* st/vdpau: Destroy context when initialization failsAaron Watry2013-12-231-0/+1
| | | | | | | | | Prevents a potential memory leak found when tracking down something else. Reviewed-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]> CC: "10.0" <[email protected]>
* radeon/llvm: Free target data at end of optimizationAaron Watry2013-12-231-0/+1
| | | | | | Reviewed-by: Tom Stellard <[email protected]> CC: "10.0" <[email protected]>
* r600/compute: Use the correct FREE macro when deleting compute stateAaron Watry2013-12-231-1/+1
| | | | | | Reviewed-by: Tom Stellard <[email protected]> CC: "10.0" <[email protected]>
* r600/compute: Free compiled kernels when deleting compute stateAaron Watry2013-12-231-0/+2
| | | | | | v2: Remove unnecessary null pointer check CC: "10.0" <[email protected]>
* radeon/compute: Stop leaking LLVMContexts in radeon_llvm_parse_bitcodeAaron Watry2013-12-235-18/+41
| | | | | | | | | | | | | | | | | | | Previously we were creating a new LLVMContext every time that we called radeon_llvm_parse_bitcode, which caused us to leak the context every time that we compiled a CL program. Sadly, we can't dispose of the LLVMContext at the point that it was being created because evergreen_launch_grid (and possibly the SI equivalent) was assuming that the context used to compile the kernels was still available. Now, we'll create a new LLVMContext when creating EG/SI compute state, store it there, and pass it to all of the places that need it. The LLVM Context gets destroyed when we delete the EG/SI compute state. Reviewed-by: Tom Stellard <[email protected]> CC: "10.0" <[email protected]>
* pipe_loader/sw: close dev->lib when initialization failsAaron Watry2013-12-231-1/+4
| | | | | | | | Prevents a memory leak. Reviewed-by: Tom Stellard <[email protected]> CC: "10.0" <[email protected]>
* clover: Remove unused variableAaron Watry2013-12-231-1/+0
| | | | | | Reviewed-by: Tom Stellard <[email protected]> CC: "10.0" <[email protected]>
* llvmpipe: use pipe_sampler_view_release() to avoid segfaultJonathan Liu2013-12-221-0/+6
| | | | | | | | | This fixes another case of faulting when freeing a pipe_sampler_view that belongs to a previously destroyed context. Cc: "10.0" <[email protected]> Signed-off-by: Jonathan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* st/mesa: use pipe_sampler_view_release()Jonathan Liu2013-12-221-1/+1
| | | | | | | | | | | | This fixes a crash where old_view->context was already freed in the pipe_sampler_view_reference function contained in src/gallium/auxiliary/utils/u_inlines.h. As a result, the sampler_view_destroy function pointer contained 0xfeeefeee indicating freed heap memory. Cc: "10.0" <[email protected]> Signed-off-by: Jonathan Liu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* i915: Add support for gl_FragData[0] reads.Henri Verbeet2013-12-221-0/+1
| | | | | | | | | | | Similar to 556a47a2621073185be83a0a721a8ba93392bedb, without this reading from gl_FragData[0] would cause a software fallback. Bugzilla: https://bugs.winehq.org/show_bug.cgi?id=33964 Signed-off-by: Henri Verbeet <[email protected]> Cc: 10.0 9.2 9.1 <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* radeonsi: Use htile_buffer for depth only when there is no stencil.Andreas Hartmetz2013-12-221-0/+8
| | | | Signed-off-by: Marek Olšák <[email protected]>
* winsys/radeon: remove superfluous distinction of casesNiels Ole Salscheider2013-12-221-15/+5
| | | | | | Signed-off-by: Niels Ole Salscheider <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* mesa: inline r200 radeon texture format macros to facility search and replaceMark Mueller2013-12-212-102/+70
| | | | | Signed-off-by: Mark Mueller <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* mesa: Fix build to properly check for supported compiler flagsLauri Kasanen2013-12-201-1/+5
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72708 Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Lauri Kasanen <[email protected]>
* mesa: It is not possible to have GLSL < 1.20Ian Romanick2013-12-202-3/+0
| | | | | | | This hasn't been possible for a long time. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Clean up bad code formatting left from previous commitIan Romanick2013-12-204-20/+18
| | | | | | | Also s/_EXT// on enums that are now part of core. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: GL_EXT_packed_depth_stencil is not optionalIan Romanick2013-12-2012-40/+11
| | | | | | | | Every driver supports it. All current and future Gallium drivers always support it, and all existing classic drivers support it. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* radeon: Sort list of enabled extensionsIan Romanick2013-12-201-6/+5
| | | | | Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r200: Sort list of enabled extensionsIan Romanick2013-12-201-16/+10
| | | | | | | Note that ARB_occlusion_query was previously enabled twice. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* glx: Simplify __glxGetMscRate, it only needs the screen, not a drawableLauri Kasanen2013-12-203-6/+4
| | | | | | | | | | Useful in its own right, but also needed for adaptive vsync. No regressions in the piglit glx-oml-sync-control-getmscrate test. Signed-off-by: Lauri Kasanen <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Tested-by: Ian Romanick <[email protected]>
* dri3: Rename DRI3_MAX_BACK to DRI3_NUM_BACKKeith Packard2013-12-202-7/+7
| | | | | | | | | It is the maximum number of back buffers, but the name is confusing and is easily read as the maximum back buffer index. Chage to DRI3_NUM_BACK to make the intended usage a bit clearer. Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Set fast color clear mcs_state on newly allocated image miptreesKeith Packard2013-12-201-3/+7
| | | | | | | | | | Just copying code from the dri2 path to set up the fast color clear state. This also removes a couple of bogus intel_region_reference calls. Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Correct check for re-bound buffer in intel_update_image_bufferKeith Packard2013-12-201-4/+15
| | | | | | | | | | | The buffer-object is the persistent thing passed through the loader, so when updating an image buffer, check to see if it is already bound to the provided bo. The region, on the other hand, is allocated separately for the miptree, and so will never be the same as that passed back from the loader. Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri3: Clean up struct dri3_drawableKeith Packard2013-12-201-5/+1
| | | | | | | | | Move the depth field up with width and height. Remove unused previous_time and frames fields. Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri3: Free resources when drawable is destroyed.Keith Packard2013-12-202-2/+20
| | | | | | | Always nice to clean up after ourselves. Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* dri3: Switch to libxshmfence version 1.1Keith Packard2013-12-202-3/+3
| | | | | | | | | | | libxshmfence v1.0 foolishly used 'int32_t *' for the fence type, which works when the fence is a linux futex. However, version 1.1 changes the exported datatype to 'struct xshmfence *' Require libxshmfence version 1.1 and switch the API around. Signed-off-by: Keith Packard <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use RED for depth texture formats rather than INTENSITY.Kenneth Graunke2013-12-201-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While looking through the documentation, I found this in the Sandybridge PRM (Volume 4, Part 1, Page 140): "Use of sample_c with SURFTYPE_CUBE surfaces is undefined with the following surface formats: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM, I32_FLOAT, L32_FLOAT, A32_FLOAT." I haven't observed this to be true, but it suggests that we may want to use other formats. We already perform DEPTH_TEXTURE_MODE swizzling in the shaders, and don't rely on the surface format to splat things appropriately. So using RED should work just as well as INTENSITY. A few notes about the formats: - R24_UNORM_X8_TYPELESS has the exact same properties as I24X8_UNORM. - R16_UNORM and R32_FLOAT are additionally supported as a render target, while the old I16_UNORM/I32_FLOAT formats are not. - R32_FLOAT_X8X24_TYPELESS is not supported as a render target, while the old format (R32G32_FLOAT) was. However, it shares the same properties as the formats we use for Z24, so it should suffice. This makes translate_tex_format and brw_blorp_surface_info::set a bit more similar. No Piglit changes on Sandybridge or Ivybridge. No oglconform changes on Sandybridge. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen6: Fix HiZ hang in WebGL Google MapsChad Versace2013-12-201-0/+15
| | | | | | | | | | | | | | | | | | | | | Emitting flushes before depth and hiz resolves at the top of blorp's state emission fixes the hang. Marchesin and I found the fix experimentally, as opposed to adhering to a documented hardware workaround. A more minimal fix likely exists, but this gets the job done. Fixes HiZ hangs in the new WebGL Google maps on Sandybridge Chrome OS. Tested by zooming in and out continuously for 2 hours. This patch is based on https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/8bc07bb70163c3706fb4ba5f980e57dc942f56dd CC: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70740 Signed-off-by: Stéphane Marchesin <[email protected]> Signed-off-by: Chad Versace <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Store QPitch in intel_mipmap_tree.Kenneth Graunke2013-12-202-6/+10
| | | | | | | | | | | | | | | Broadwell allows us to specify an arbitrary value for QPitch, rather than baking a specific formula into the hardware and requiring software to lay things out to match. The only restriction is that the software provided QPitch needs to be large enough so successive array slices do not overlap. In order to support this flexibility, software needs to specify QPitch in a bunch of packets. Storing QPitch makes that easy, and allows us to adjust it in a single place should we wish to change it in the future. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add support for Broadwell's new register types.Kenneth Graunke2013-12-203-1/+19
| | | | | | | | | | | | Broadwell introduces support for Q, UQ, and HF types. It also extends DF support to allow immediate values. Irritatingly, although HF and DF both support immediates, they're represented by a different value depending on the register file. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Add BRW_REGISTER_TYPE_DF.Kenneth Graunke2013-12-203-0/+6
| | | | | | | | | Ivybridge, Baytrail, and Haswell support double float register types, but do not support them as immediate values. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values.Kenneth Graunke2013-12-204-22/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | On released hardware, values 4-6 are overloaded. For normal registers, they mean UB/B/DF. But for immediates, they mean UV/VF/V. Previously, we just created #defines for each name, reusing the same value. This meant we could directly splat the brw_reg::type field into the assembly encoding, which was fairly nice, and worked well. Unfortunately, Broadwell makes this infeasible: the HF and DF types are represented as different numeric values depending on whether the source register is an immediate or not. To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to an abstract enum that has a unique value for each register type, and write translation functions. One nice benefit is that we can add assertions about register files and generations. I've chosen not to convert brw_reg::type to the enum, since converting it caused a lot of trouble due to C++ enum rules (even though it's defined in an extern "C" block...). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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