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* radeonsi: use SDMA for uploading data through const_uploaderMarek Olšák2019-02-205-28/+143
| | | | | | | | v2: use tc.stream_uploader in si buffer_transfer_map if not called from the driver thread Reviewed-by: Nicolai Hähnle <[email protected]> (v1) Tested-by: Dieter Nützel <[email protected]>
* gallium/u_upload_mgr: allow use of FLUSH_EXPLICIT with persistent mappingsMarek Olšák2019-02-202-6/+31
| | | | | | | for radeonsi Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium/u_threaded: always unmap const_uploaderMarek Olšák2019-02-201-0/+1
| | | | | | | | radeonsi will require this. It's a no-op for drivers supporting persistent mappings. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* st/mesa: always unmap the uploader in st_atom_array.cMarek Olšák2019-02-201-8/+6
| | | | | | | This is a no-op for drivers supporting persistent mappings. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* nir/xfb: Handle compact arrays in gather_xfb_infoJason Ekstrand2019-02-211-11/+22
| | | | | | | This makes us properly handle gl_ClipDistance and gl_CullDistance. Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info" Reviewed-by: Alejandro Piñeiro <[email protected]>
* nir/xfb: Work in terms of components rather than slotsJason Ekstrand2019-02-211-5/+5
| | | | | | | | | | | | | | | | | | We needed to better handle cases where a chunk of a variable starts at some non-zero location_frac and rolls over into the next slot but may not be more than 4 dwords. For example, if gl_CullDistance is an array of 3 things and has location_frac = 2, it will span across two vec4s but is not, itself, bigger than a vec4. If you ignore the clip/cull special case, it's not allowed to happen for anything else because the only things that can span more than one slot is dvec3 and dvec4 and they're both bigger than a vec4. The current code uses this attrib_slot thing where we count attribute slots and iterate over them. However, that doesn't work in the case above because gl_CullDistance will have an attrib_slot count of 1 even though it does span two slots. We could fix this by adjusting attrib_slot but we already have comp_mask and it's easier to just handle it that way. Reviewed-by: Alejandro Piñeiro <[email protected]>
* nir: Rewrite lower_clip_cull_distance_arrays to do a lot less loweringJason Ekstrand2019-02-211-113/+19
| | | | | | | | | | Instead of going to all the work of to combine them into one array, just make two arrays and use location_frac to colocate them within CLIP0. Then the back-end can sort things out and stack them on top of each other. Thanks to ef99f4c8, we also don't need to set compact anymore. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/xfb: Properly align 64-bit valuesJason Ekstrand2019-02-211-0/+4
| | | | | Fixes: 19064b8c "nir: Add a pass for gathering transform feedback info" Reviewed-by: Alejandro Piñeiro <[email protected]>
* compiler/types: Add a contains_64bit helperJason Ekstrand2019-02-214-0/+29
| | | | Reviewed-by: Alejandro Piñeiro <[email protected]>
* freedreno/a6xx: samplerBuffer fixesRob Clark2019-02-203-8/+17
| | | | | | | | | | | | | | Use the 'UNK31' bit (which should probably be called 'BUFFER') for samplerBuffer case, which increases the size of supported buffer texture beyond 2^15 elements. Also need to fix the 2nd coord injected to handle the tex instructions that take integer coords. Fixes dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071 and similar Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/a6xx: use ldib for ssbo readsRob Clark2019-02-201-24/+10
| | | | | | | | | | | | | ... instead of isam. It seems like when using isam, plus atomics, we can have the problem of old data being in the texture cache. Plus this way we don't have to load a component at a time. Note that blob still seems to use isam in some cases. I suppose it might be preferable in the case of loading a single component, when atomics are not in the picture (or that the ssbo does not need to otherwise be coherent). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: sync instr/disasm and add ldib encodingRob Clark2019-02-204-14/+42
| | | | | | | | | | Resync disasm and instr header from envytools, and add ldib encoding. This replaces an opcode from a3xx which was never seen in practice, since that seemed easier than dealing with the same opc # meaning a different thing on a6xx. (Not really sure if 'sti' was actually a real thing, I think it was only seen in fuzzing.) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3/a6xx: fix load_ssbo barrier type.Rob Clark2019-02-201-2/+2
| | | | | | | Silly copy/pasta bug, since load_image is actually the same instruction but different barrier class. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rename put_dst()Rob Clark2019-02-203-9/+9
| | | | | | | This was overlooked when it moved to ir3_context.c and ceased to be static.. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix crash w/ masked non-SSA dstRob Clark2019-02-201-0/+2
| | | | | | | | | Fixes dEQP-GLES3.functional.shaders.indexing.varying_array.vec3_dynamic_write_dynamic_loop_read regression. Fixes: c1a27ba9baf freedreno/ir3: HIGH reg w/a for a6xx Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: 3d and cube image fixesRob Clark2019-02-201-4/+31
| | | | | | | Fixes dEQP-GLES31.functional.image_load_store.{3d,cube}.store.* and a bunch more Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crash in compile fail caseRob Clark2019-02-203-6/+9
| | | | | | | The variant will be NULL if RA failed. Which isn't ideal, but at least lets not segfault and bring down the rest of the dEQP run with us. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix legalize for vecN inputsRob Clark2019-02-202-0/+3
| | | | | | | | | The wrmask is handled in regmask_get()/regmask_set(), but it wasn't being propagated from SSA src to dst. So for example, an SSBO read value that is passed in as src2.y component to atomic op, wasn't getting the (sy) flag set. Causing lots of fail. Signed-off-by: Rob Clark <[email protected]>
* radv: Disable depth clamping even without EXT_depth_range_unrestricted.Bas Nieuwenhuizen2019-02-201-2/+1
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Implement VK_EXT_depth_clip_enable.Bas Nieuwenhuizen2019-02-203-2/+16
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: remove non-ssa support from nir_copy_prop()Timothy Arceri2019-02-211-36/+5
| | | | | | | | | Even in a very basic shader this reduces the time spent in nir_copy_prop() by ~17%. No shader-db changes for radeonsi NIR or i965. Reviewed-by: Jason Ekstrand <[email protected]>
* radv: Handle clip+cull distances more generally as compact arrays.Bas Nieuwenhuizen2019-02-204-99/+83
| | | | | | | | | | | | Needed for https://gitlab.freedesktop.org/mesa/mesa/merge_requests/248 . That MR keeps the clip and cull arrays split. So we have to handle - compact arrays with location_frac != 0 - VARYING_SLOT_CLIP_DIST1 Reviewed-by: Samuel Pitoiset <[email protected]>
* kmsro: Add the rest of the current set of tinydrm drivers.Eric Anholt2019-02-204-7/+33
| | | | | | | | | | | While I haven't tested them all, given that they're all using the same allocation paths and modifiers in the kernel they should be fine to use in the same way. v2: Rebase on other kmsro changes. v3: Skip repeated '[with_gallium_kmsro,' in the meson build. Acked-by: Alyssa Rosenzweig <[email protected]>
* i965: re-emit index buffer state on a reset option change.Andrii Simiklit2019-02-203-1/+13
| | | | | | | | | | | | | | Seems like we forget to update the index buffer (ib) status and IndexedDrawCutIndexEnable or CutIndexEnable flag is left unchanged it leads to ignoring of glEnable/glDisable functions for GL_PRIMITIVE_RESTART in some cases. The index buffer (ib) status should be re-emmited after the reset option change to avoid some unexpected behavior. Reviewed-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109451 Cc: <[email protected]> Signed-off-by: Andrii Simiklit <[email protected]> Signed-off-by: Andrii Simiklit <[email protected]>
* nir: Don't forget if-uses in new nir_opt_dead_cf liveness checkKenneth Graunke2019-02-201-0/+10
| | | | | | | | | | | | | | | | Commit 08bfd710a25c14df5f690cce9604617536d7c560. (nir/dead_cf: Stop relying on liveness analysis) introduced a new check that iterated through a SSA def's uses, to see if it's used. But it only checked normal uses, and not uses which are part of an 'if' condition. This led to it thinking more nodes were dead than possible. Fixes Piglit's variable-indexing/tcs-output-array-float-index-wr test (and related tests) with the out-of-tree Iris driver. Fixes: 08bfd710a25 nir/dead_cf: Stop relying on liveness analysis Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* freedreno/a6xx: Support MSAA resolve blits on blitterKristian H. Kristensen2019-02-201-3/+23
| | | | | | | | | | | | | | | This gets stencil and depth resolves working properly. Fixes: dEQP-GLES3.functional.fbo.msaa.2_samples.depth32f_stencil8 dEQP-GLES3.functional.fbo.msaa.2_samples.depth24_stencil8 dEQP-GLES3.functional.fbo.msaa.4_samples.depth32f_stencil8 dEQP-GLES3.functional.fbo.msaa.4_samples.depth24_stencil8 dEQP-GLES3.functional.fbo.invalidate.whole.unbind_blit_msaa_color dEQP-GLES3.functional.fbo.invalidate.sub.unbind_blit_msaa_color Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno/a6xx: Copy stencil as R8_UINTKristian H. Kristensen2019-02-201-4/+14
| | | | | | | | | | | Blitter does support it after all. Previous attempt to use R8_UINT failed because we overwrote the a6xx format in emit_blit_texture(), but some of the later setup still looked at the gallium format. If we overwrite it in the pipe_blit_info before we even call into emit_blit_texture() it works properly. Signed-off-by: Kristian H. Kristensen <[email protected]>
* freedreno: Update headersKristian H. Kristensen2019-02-207-7/+13
| | | | | | Add support for multisampled sources for the blitter. Signed-off-by: Kristian H. Kristensen <[email protected]>
* anv: use anv_shader_bin_write_to_blob()'s return valueEric Engestrom2019-02-201-3/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: drop unused importsEric Engestrom2019-02-201-2/+0
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: make sure the extensions stay sortedEric Engestrom2019-02-201-0/+20
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: sort vendors extensions after KHR and EXTEric Engestrom2019-02-201-2/+2
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: sort extensions alphabeticallyEric Engestrom2019-02-201-1/+1
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* anv: anv: refactor error handling in anv_shader_bin_write_to_blob()Tapani Pälli2019-02-201-28/+26
| | | | | | | | | | v2: blob manages error state internally, just return true if errors did not occur (Jason) CID: 1442546 Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* wayland/egl: Ensure EGL surface is resized on DRI update_buffers()Carlos Garnacho2019-02-201-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fullscreening and unfullscreening a totem window while playing a video sometimes results in the video subsurface not changing size along. This is also reproducible with epiphany. If a surface gets resized while we have an active back buffer for it, the resized dimensions won't get neither immediately applied on the resize callback, nor correctly synchronized on update_buffers(), as the (now stale) surface size and currently attached buffer size still do match. There's actually 2 things to synchronize here, first the surface query size might not be updated yet to the wl_egl_window's (i.e. resize_callback happened while there is a back buffer), and second the wayland buffers would need dropping if new surface size differs with the currently attached buffer. These are done in separate steps now. https://bugzilla.redhat.com/show_bug.cgi?id=1650929 https://bugs.freedesktop.org/show_bug.cgi?id=109594 Fixes: a9fb331ea7d ("wayland/egl: update surface size on window resize") Signed-off-by: Carlos Garnacho <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]> Reviewed-by: Daniel Stone <[email protected]> Tested-by: Bastien Nocera <[email protected]> Tested-by: Denys Kostin <[email protected]>
* anv: implement VK_EXT_depth_clip_enableLionel Landwerlin2019-02-205-4/+23
| | | | | | | A new extension allowing the user to explictly specify the clipping behavior. Signed-off-by: Lionel Landwerlin <[email protected]>
* vulkan: Update the XML and headers to 1.1.101Lionel Landwerlin2019-02-201-32/+169
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* isl: remove the cache line size alignment requirementSamuel Iglesias Gonsálvez2019-02-201-14/+0
| | | | | | | | | | | | The cacheline size was a requirement for using the BLT engine, which we don't use anymore except for a few things on old HW, so we drop it. Fixes CTS's CL#3500 test: dEQP-VK.api.image_clearing.core.clear_color_image.2d.linear.single_layer.r8g8b8_unorm Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: Clean up a bunch of compiler warnings.Bas Nieuwenhuizen2019-02-203-7/+0
| | | | | | Random unused vars. Reviewed-by: Timothy Arceri <[email protected]>
* radv: Sync ETC2 whitelisted devices.Bas Nieuwenhuizen2019-02-203-5/+11
| | | | | Fixes: 4bb6c49375e "radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9." Reviewed-by: Dave Airlie <[email protected]>
* st/nir: use NIR for asm programsTimothy Arceri2019-02-192-1/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses prog_to_nir to translate ARB assembly programs to NIR. Co-authored by Tim Arceri, Dave Airlie, and Ken Graunke: - [Tim Arceri]: original patch - [Dave Airlie]: fix crashes with parameter names - [Ken Graunke]: - Rebase on SCALAR_ISA cap, lower wpos_ytransform too. - Rebase on streamout fixes. - Lower system values for fragcoord support. - Don't try to use prog_to_nir for ATI_fragment_shader programs. - Create TGSI for fixed-function or ARB vertex shaders even if the driver prefers NIR, so we can create draw module shaders for feedback/select emulation, which rely on TGSI. Tested on: - iris (Intel Skylake/Kabylake): Piglit & GL CTS - Ken Graunke - radeonsi (AMD Vega 64): Piglit - Ken Graunke - vc4/v3d - Piglit - Eric Anholt - freedreno - dEQP - Kristian Høgsberg Fixes lit_degenerate_case on vc4 and v3d, and vp-address-01, vp-arl-constant-array-huge-offset-neg, and vp-arl-neg-array on v3d. No Piglit regressions on radeonsi; no dEQP regressions on freedreno. Acked-by: Eric Anholt <[email protected]> Tested-by: Eric Anholt <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: Copy VP TGSI tokens if they exist, even for NIR shaders.Kenneth Graunke2019-02-191-2/+8
| | | | | | | | | | | | Even if the driver wants to use NIR shaders, we may need to have TGSI tokens for creating draw module vertex shaders for the feedback/select render modes. So...if the st_vertex_program has any TGSI...copy it to the variant. Acked-by: Eric Anholt <[email protected]> Tested-by: Eric Anholt <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: Go back to using llvm.pow intrinsic for nir_op_fpowKenneth Graunke2019-02-192-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARB_vertex_program and ARB_fragment_program define 0^0 = 1 (while GLSL leaves it undefined). Performing fpow lowering in NIR would break this behavior, preventing us from using prog_to_nir. According to llvm/lib/Target/AMDGPU/SIInstructions.td, POW_common expands to <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>, which presumably does a zero-wins multiply. Lowering in NIR results in a non-legacy multiply, where: pow(0, 0) = 2^(log2(0) * 0) = 2^(-INF * 0) = 2^(-NaN) = -NaN which isn't the desired result. This reverts: - commit d6b75392067712908bdc372f1007e085439bf9f5 (ac/nir: remove emission of nir_op_fpow) - commit 22430224fec31591432d4a3e65c6f457ba1c1653 (radeonsi/nir: enable lowering of fpow) and prevents a regression in gl-1.0-spot-light with AMD_DEBUG=nir after enabling prog_to_nir in st/mesa later in this series. Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi/nir: set shader_buffers_declared properlyTimothy Arceri2019-02-201-10/+22
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: set colors_read properlyTimothy Arceri2019-02-201-7/+10
| | | | | | | | | | | | | | | | | | shader-db results for VEGA64: Totals from affected shaders: SGPRS: 1976 -> 1976 (0.00 %) VGPRS: 1240 -> 1144 (-7.74 %) Spilled SGPRs: 145 -> 145 (0.00 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 34632 -> 34604 (-0.08 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 261 -> 285 (9.20 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: set input_usage_mask properlyTimothy Arceri2019-02-201-11/+36
| | | | | | | | | | | | | | | | | | shader-db results for VEGA64: Totals from affected shaders: SGPRS: 791528 -> 792616 (0.14 %) VGPRS: 421624 -> 410784 (-2.57 %) Spilled SGPRs: 1639 -> 1674 (2.14 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 0 -> 0 (0.00 %) dwords per thread Code Size: 16103516 -> 16063696 (-0.25 %) bytes LDS: 0 -> 0 (0.00 %) blocks Max Waves: 136307 -> 137830 (1.12 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: Use uniform location when calculating const_file_max.Timur Kristóf2019-02-201-6/+6
| | | | | | | | | | | The nine state tracker can produce NIR uniform variables whose location is explicitly set. radeonsi did not take that into account when calculating const_file_max, resulting in rendering glitches. This patch fixes that. Signed-Off-By: Timur Kristóf <[email protected]> Tested-by: Andre Heider <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* drirc: Add sddm-greeter to adaptive_sync blacklist.Mario Kleiner2019-02-191-0/+3
| | | | | | | | | This is the sddm login screen. Fixes: a9c36dbf9c56 ("drirc: Initial blacklist for adaptive sync") Signed-off-by: Mario Kleiner <[email protected]> Cc: 19.0 <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* driconf: add Civ6Sub executable for Civilization 6Marek Olšák2019-02-191-0/+6
| | | | | | | I'm getting Civ6Sub instead of Civ6. Cc: 18.3 19.0 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: always enable NIR for Civilization 6 to fix corruptionMarek Olšák2019-02-191-0/+3
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104602 Cc: 18.3 19.0 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
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