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* anv/apply_pipeline_layout: Handle separate samplers and texturesJason Ekstrand2015-11-141-17/+73
* Merge branch 'wip/i965-separate-sampler-tex' into vulkanJason Ekstrand2015-11-1416-74/+181
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| * i965/vec4: Plumb separate surfaces and samplers through from NIRJason Ekstrand2015-11-143-13/+30
| * i965/vec4: Separate the sampler from the surface in generate_texJason Ekstrand2015-11-141-5/+13
| * i965/fs: Plumb separate surfaces and samplers through from NIRJason Ekstrand2015-11-146-36/+60
| * i965/fs: Separate the sampler from the surface in generate_texJason Ekstrand2015-11-142-6/+15
| * nir: Separate texture from sampler in nir_tex_instrJason Ekstrand2015-11-148-17/+66
* | Merge remote-tracking branch 'mesa-public/master' into vulkanJason Ekstrand2015-11-14328-4365/+8838
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| * nouveau: don't expose HEVC decoding supportIlia Mirkin2015-11-141-0/+1
| * nir: Silence GCC maybe-uninitialized warnings.Vinson Lee2015-11-131-0/+3
| * i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-134-5/+10
| * glsl: Allow implicit int -> uint conversions for the % operator.Kenneth Graunke2015-11-131-9/+28
| * i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.Kenneth Graunke2015-11-134-1/+40
| * i965: Make convert_attr_sources_to_hw_regs handle stride == 0.Kenneth Graunke2015-11-131-1/+2
| * nir: Add helpers for getting input/output intrinsic sources.Kenneth Graunke2015-11-132-0/+45
| * nir: Don't lower TCS outputs to temporaries.Kenneth Graunke2015-11-131-0/+3
| * nir: Allow outputs reads and add the relevant intrinsics.Kenneth Graunke2015-11-134-8/+21
| * nir/lower_io: Introduce nir_store_per_vertex_output intrinsics.Kenneth Graunke2015-11-133-5/+26
| * nir/lower_io: Use load_per_vertex_input intrinsics for TCS and TES.Kenneth Graunke2015-11-131-4/+8
| * i965: Silence unused parameter warnings in get_buffer_rectIan Romanick2015-11-131-4/+3
| * meta/generate_mipmap: Don't leak the sampler objectIan Romanick2015-11-131-0/+2
| * i965: Remove unneeded #includes.Matt Turner2015-11-131-4/+0
| * i965: Silence warning.Matt Turner2015-11-131-2/+2
| * i965: Don't write beyond allocated memory.Juha-Pekka Heikkila2015-11-131-1/+1
| * i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-134-6/+6
| * i965: Combine register file field.Matt Turner2015-11-137-34/+27
| * i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-1313-211/+157
| * i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).Matt Turner2015-11-131-0/+6
| * i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().Matt Turner2015-11-131-0/+3
| * i965: Rename GRF to VGRF.Matt Turner2015-11-1330-194/+194
| * i965: Move BAD_FILE from the beginning of enum register_file.Matt Turner2015-11-131-1/+1
| * i965: Initialize registers.Matt Turner2015-11-133-2/+18
| * i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-1325-290/+276
| * i965: Unwrap some lines.Matt Turner2015-11-134-12/+4
| * i965/vec4: Remove swizzle/writemask fields from src/dst_reg.Matt Turner2015-11-132-8/+1
| * i965: Remove fixed_hw_reg field from backend_reg.Matt Turner2015-11-1311-162/+139
| * i965: Use immediate storage in inherited brw_reg.Matt Turner2015-11-1310-95/+96
| * i965: Add and use enum brw_reg_file.Matt Turner2015-11-134-19/+23
| * i965: Reorganize brw_reg fields.Matt Turner2015-11-131-8/+8
| * i965: Make 'dw1' and 'bits' unnamed structures in brw_reg.Matt Turner2015-11-1314-178/+185
| * i965: Delete type field from backend_reg.Matt Turner2015-11-131-1/+0
| * i965: Delete abs/negate fields from backend_reg.Matt Turner2015-11-133-5/+2
| * i965: Make backend_reg inherit from brw_reg.Matt Turner2015-11-131-3/+3
| * i965/fs: Replace nested ternary with if ladder.Matt Turner2015-11-131-6/+7
| * radeonsi: remove dead code after ES-GS linkage changeMarek Olšák2015-11-133-57/+0
| * radeonsi: link ES-GS just like LS-HSMarek Olšák2015-11-133-39/+19
| * radeonsi: calculate optimal GS ring sizes to fix GS hangs on TongaMarek Olšák2015-11-135-47/+113
| * radeonsi: rename si_update_gs_ringsMarek Olšák2015-11-131-2/+2
| * radeonsi: calculate ESGS_RING_ITEMSIZE in create_shaderMarek Olšák2015-11-132-1/+3
| * radeonsi: move maximum gs stream calculation into create_shaderMarek Olšák2015-11-132-16/+7
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