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* anv/cmd_buffer: Add a new genX_cmd_buffer file for shared codeJason Ekstrand2015-11-186-449/+286
| | | | | | | | | | | This file contains code that can be shared across gens modulo recompiling. In particular, we can share STATE_BASE_ADDRESS setup and handling of the vkPipelineBarrier call. Not sharing STATE_BASE_ADDRESS setup has already been a source of bugs and the gen7 and gen8 implementations of PipelineBarrier were line-for-line identical. Incidentally, this should fix MOCS settings for dynamic and surface state on Haswell.
* anv/gen7: A bunch of depth-stencil fixesJason Ekstrand2015-11-183-13/+15
| | | | | | There are various bits which move around between Haswell and Ivy Bridge that we weren't taking into account. This also makes us actually set the StencilWriteEnable in a sane way.
* gen7/pipeline: Re-arrange stencil parameters to match gen8Jason Ekstrand2015-11-171-11/+10
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* anv/gen7: Implement CmdPipelineBarrierJason Ekstrand2015-11-171-1/+128
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* anv/gen7: Don't use the upper bound on dynamic state base addressJason Ekstrand2015-11-171-3/+0
| | | | | It doesn't do much for us and, if we have to resize the dynamic state block pool for any reason, it becomes out-of-date.
* anv: Add initial Haswell supportJason Ekstrand2015-11-178-77/+171
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* anv: Add macros for doing per-gen compilationJason Ekstrand2015-11-172-11/+169
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* anv/entrypoints: Add dispatch support for haswellJason Ekstrand2015-11-171-1/+5
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* anv/entrypoints: Use devinfo instead of a gen numberJason Ekstrand2015-11-172-6/+11
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* anv/cmd_buffer: Pack the 3DSTATE_VF packet on-demandJason Ekstrand2015-11-174-16/+12
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* anv/formats: Don't advertise stencil texture/blit prior to BroadwellJason Ekstrand2015-11-171-2/+4
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* anv: Only include the pack headers where neededJason Ekstrand2015-11-1612-27/+46
| | | | | | | Previously, we were including gen7_pack.h, gen75_pack.h, and gen8_pack.h in anv_private.h. As we add more gens, this is going to become untenable. This commit moves things around so that we only use the pack headers when and if we need them.
* anv/cmd_buffer: Move gen-specific stuff into the appropreate filesJason Ekstrand2015-11-164-236/+240
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* nir/spirv: Add support for separate samplers and texturesJason Ekstrand2015-11-142-16/+87
| | | | | | | This gets tricky in a few places because we have to pass vtn_sampled_image values through OpAccessChain, but it works ok. At some point, it probably needs to be cleaned up but it doesn't occur to me exactly how to do that at the moment. We'll see how this approach goes.
* anv/cmd_buffer: Add a default descriptor type caseJason Ekstrand2015-11-141-0/+4
| | | | This silences a bunch of compiler warnings.
* anv/apply_pipeline_layout: Handle separate samplers and texturesJason Ekstrand2015-11-141-17/+73
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* Merge branch 'wip/i965-separate-sampler-tex' into vulkanJason Ekstrand2015-11-1416-74/+181
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| * i965/vec4: Plumb separate surfaces and samplers through from NIRJason Ekstrand2015-11-143-13/+30
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| * i965/vec4: Separate the sampler from the surface in generate_texJason Ekstrand2015-11-141-5/+13
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| * i965/fs: Plumb separate surfaces and samplers through from NIRJason Ekstrand2015-11-146-36/+60
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| * i965/fs: Separate the sampler from the surface in generate_texJason Ekstrand2015-11-142-6/+15
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| * nir: Separate texture from sampler in nir_tex_instrJason Ekstrand2015-11-148-17/+66
| | | | | | | | | | | | | | | | | | This commit adds the capability to NIR to support separate textures and samplers. As it currently stands, glsl_to_nir only sets the sampler and leaves the texture alone as it did before and nir_lower_samplers assumes this. However, backends can, if they wish, assume that they are separate because nir_lower_samplers sets both texture and sampler index (they are the same in this case).
* | Merge remote-tracking branch 'mesa-public/master' into vulkanJason Ekstrand2015-11-14328-4365/+8838
|\| | | | | | | This pulls in Matt's big compiler refactor.
| * nouveau: don't expose HEVC decoding supportIlia Mirkin2015-11-141-0/+1
| | | | | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected]
| * nir: Silence GCC maybe-uninitialized warnings.Vinson Lee2015-11-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | nir/nir_control_flow.c: In function ‘split_block_cursor.isra.11’: nir/nir_control_flow.c:460:15: warning: ‘after’ may be used uninitialized in this function [-Wmaybe-uninitialized] *_after = after; ^ nir/nir_control_flow.c:458:16: warning: ‘before’ may be used uninitialized in this function [-Wmaybe-uninitialized] *_before = before; ^ Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
| * i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-134-5/+10
| | | | | | | | | | | | | | | | | | | | | | We need to use per-slot offsets when there's non-uniform indexing, as each SIMD channel could have a different index. We want to use them for any non-constant index (even if uniform), as it lives in the message header instead of the descriptor, allowing us to set offsets in GRFs rather than immediates. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]>
| * glsl: Allow implicit int -> uint conversions for the % operator.Kenneth Graunke2015-11-131-9/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GLSL 4.00 and GL_ARB_gpu_shader5 introduced a new int -> uint implicit conversion rule and updated the rules for modulus to use them. (In earlier languages, none of the implicit conversion rules did anything relevant, so there was no point in applying them.) This allows expressions such as: int foo; uint bar; uint mod = foo % bar; Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
| * i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.Kenneth Graunke2015-11-134-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | I've been carrying around a patch to do this for the last few months, and it's been exceedingly useful for debugging GS and tessellation problems. I've caught lots of bugs by inspecting the interface expectations of two adjacent stages. It's not that much spam, so I figure we may as well just print it. Signed-off-by: Kenneth Graunke <[email protected]> Acked-by: Matt Turner <[email protected]>
| * i965: Make convert_attr_sources_to_hw_regs handle stride == 0.Kenneth Graunke2015-11-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | This makes expressions like component(fs_reg(ATTR, n), 7) get a proper <0,1,0> region instead of the invalid <0,8,0>. Nobody uses this today, but I plan to. v2: Rebase on Matt's changes; simplify. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> [v1]
| * nir: Add helpers for getting input/output intrinsic sources.Kenneth Graunke2015-11-132-0/+45
| | | | | | | | | | | | | | | | | | | | With the many variants of IO intrinsics, particular sources are often in different locations. It's convenient to say "give me the indirect offset" or "give me the vertex index" and have it just work, without having to think about exactly which kind of intrinsic you have. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
| * nir: Don't lower TCS outputs to temporaries.Kenneth Graunke2015-11-131-0/+3
| | | | | | | | | | | | | | | | We'd like to shadow these when possible, but the current code doesn't work properly for TCS outputs. For now, disable it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
| * nir: Allow outputs reads and add the relevant intrinsics.Kenneth Graunke2015-11-134-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally, we rely on nir_lower_outputs_to_temporaries to create shadow variables for outputs, buffering the results and writing them all out at the end of the program. However, this is infeasible for tessellation control shader outputs. Tessellation control shaders can generate multiple output vertices, and write per-vertex outputs. These are arrays indexed by the vertex number; each thread only writes one element, but can read any other element - including those being concurrently written by other threads. The barrier() intrinsic synchronizes between threads. Even if we tried to shadow every output element (which is of dubious value), we'd have to read updated values in at barrier() time, which means we need to allow output reads. Most stages should continue using nir_lower_outputs_to_temporaries(), but in theory drivers could choose not to if they really wanted. v2: Rebase to accomodate Jason's review feedback. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
| * nir/lower_io: Introduce nir_store_per_vertex_output intrinsics.Kenneth Graunke2015-11-133-5/+26
| | | | | | | | | | | | | | | | | | | | | | Similar to nir_load_per_vertex_input, but for outputs. This is not useful in geometry shaders, but will be useful in tessellation shaders. v2: Change stage_uses_per_vertex_outputs() to is_per_vertex_output(), taking a nir_variable (requested by Jason Ekstrand). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
| * nir/lower_io: Use load_per_vertex_input intrinsics for TCS and TES.Kenneth Graunke2015-11-131-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tessellation control shader inputs are an array indexed by the vertex number, like geometry shader inputs. There aren't per-patch TCS inputs. Tessellation evaluation shaders have both per-vertex and per-patch inputs. Per-vertex inputs get the new intrinsics; per-patch inputs continue to use the ordinary load_input intrinsics, as they already work like we want them to. v2: Change stage_uses_per_vertex_inputs into is_per_vertex_input(), which takes a variable (requested by Jason Ekstrand). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
| * i965: Silence unused parameter warnings in get_buffer_rectIan Romanick2015-11-131-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | brw_meta_fast_clear.c: In function 'get_buffer_rect': brw_meta_fast_clear.c:318:37: warning: unused parameter 'brw' [-Wunused-parameter] get_buffer_rect(struct brw_context *brw, struct gl_framebuffer *fb, ^ brw_meta_fast_clear.c:319:44: warning: unused parameter 'irb' [-Wunused-parameter] struct intel_renderbuffer *irb, struct rect *rect) ^ Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
| * meta/generate_mipmap: Don't leak the sampler objectIan Romanick2015-11-131-0/+2
| | | | | | | | | | | | Signed-off-by: Ian Romanick <[email protected]> Cc: "10.6 11.0" <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
| * i965: Remove unneeded #includes.Matt Turner2015-11-131-4/+0
| | | | | | | | | | Some of these are no longer needed since all the backends switched to NIR.
| * i965: Silence warning.Matt Turner2015-11-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | intel_asm_annotation.c: In function ‘annotation_insert_error’: intel_asm_annotation.c:214:18: warning: ‘ann’ may be used uninitialized in this function [-Wmaybe-uninitialized] ann->error = ralloc_strdup(annotation->mem_ctx, error); ^ I initially tried changing the type of ann_count to unsigned (is currently int), since that in addition to the check that it's non-zero at the beginning of the function seems sufficient to prove that it must be greater than zero. Unfortunately that wasn't sufficient.
| * i965: Don't write beyond allocated memory.Juha-Pekka Heikkila2015-11-131-1/+1
| | | | | | | | | | | | Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Juha-Pekka Heikkila <[email protected]>
| * i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-134-6/+6
| | | | | | | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965: Combine register file field.Matt Turner2015-11-137-34/+27
| | | | | | | | | | | | | | | | The first four values (2-bits) are hardware values, and VGRF, ATTR, and UNIFORM remain values used in the IR. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-1313-211/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW_REGs are (were!) kind of awful. If the file was HW_REG, you had to look at different fields for type, abs, negate, writemask, swizzle, and a second file. They also caused annoying problems like immediate sources being considered scheduling barriers (commit 6148e94e2) and other such nonsense. Instead use ARF/FIXED_GRF/MRF for fixed registers in those files. After a sufficient amount of time has passed since "GRF" was used, we can rename FIXED_GRF -> GRF, but doing so now would make rebasing awful. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).Matt Turner2015-11-131-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fs_reg() constructors for immediates set stride to 0, except for vector-immediates, which set stride to 1. This patch makes the fs_reg constructor that takes a brw_reg do likewise, so that stride is set correctly for cases such as fs_reg(brw_imm_v(...)). The generator asserts that this is true (and presumably it's useful in some optimization passes?) and the VF fs_reg constructors did this (by virtue of the fact that it doesn't override what init() does). In the next commit, calling this constructor with brw_imm_* will generate an IMM file register rather than a HW_REG, making this change necessary to avoid breakage with existing uses of brw_imm_v(). Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().Matt Turner2015-11-131-0/+3
| | | | | | | | | | | | | | | | | | We use brw_imm_v() to produce type-V immediates, which generates a brw_reg with fs_reg's .file set to HW_REG. The next commit will rid us of HW_REGs, so we need to handle BRW_REGISTER_TYPE_V in the IMM case. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965: Rename GRF to VGRF.Matt Turner2015-11-1330-194/+194
| | | | | | | | | | | | | | | | | | | | The 2-bit hardware register file field is ARF, GRF, MRF, IMM. Rename GRF to VGRF (virtual GRF) so that we can reuse the GRF name to mean an assigned general purpose register. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965: Move BAD_FILE from the beginning of enum register_file.Matt Turner2015-11-131-1/+1
| | | | | | | | | | | | | | | | | | I'm going to begin using brw_reg's file field in backend_reg and its derivatives, and in order to keep the hardware value for ARF as 0, we have to do something different. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965: Initialize registers.Matt Turner2015-11-133-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | The test (file == BAD_FILE) works on registers for which the constructor has not run because BAD_FILE is zero. The next commit will move BAD_FILE in the enum so that it's no longer zero. In the case of this->outputs, the constructor was being run implicitly, and we were unnecessarily memsetting is to zero. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-1325-290/+276
| | | | | | | | | | | | | | | | | | | | | | | | In addition to combining another field, we get replace silliness like "reg.reg" with something that actually makes sense, "reg.nr"; and no one will ever wonder again why dst.reg isn't a dst_reg. Moving the now 16-bit nr field to a 16-bit boundary decreases code size by about 3k. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965: Unwrap some lines.Matt Turner2015-11-134-12/+4
| | | | | | | | | | Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
| * i965/vec4: Remove swizzle/writemask fields from src/dst_reg.Matt Turner2015-11-132-8/+1
| | | | | | | | | | | | | | | | Also allows us to handle HW_REGs in the swizzle() and writemask() functions. Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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