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* anv/cmd_buffer: Add a new genX_cmd_buffer file for shared codeJason Ekstrand2015-11-186-449/+286
* anv/gen7: A bunch of depth-stencil fixesJason Ekstrand2015-11-183-13/+15
* gen7/pipeline: Re-arrange stencil parameters to match gen8Jason Ekstrand2015-11-171-11/+10
* anv/gen7: Implement CmdPipelineBarrierJason Ekstrand2015-11-171-1/+128
* anv/gen7: Don't use the upper bound on dynamic state base addressJason Ekstrand2015-11-171-3/+0
* anv: Add initial Haswell supportJason Ekstrand2015-11-178-77/+171
* anv: Add macros for doing per-gen compilationJason Ekstrand2015-11-172-11/+169
* anv/entrypoints: Add dispatch support for haswellJason Ekstrand2015-11-171-1/+5
* anv/entrypoints: Use devinfo instead of a gen numberJason Ekstrand2015-11-172-6/+11
* anv/cmd_buffer: Pack the 3DSTATE_VF packet on-demandJason Ekstrand2015-11-174-16/+12
* anv/formats: Don't advertise stencil texture/blit prior to BroadwellJason Ekstrand2015-11-171-2/+4
* anv: Only include the pack headers where neededJason Ekstrand2015-11-1612-27/+46
* anv/cmd_buffer: Move gen-specific stuff into the appropreate filesJason Ekstrand2015-11-164-236/+240
* nir/spirv: Add support for separate samplers and texturesJason Ekstrand2015-11-142-16/+87
* anv/cmd_buffer: Add a default descriptor type caseJason Ekstrand2015-11-141-0/+4
* anv/apply_pipeline_layout: Handle separate samplers and texturesJason Ekstrand2015-11-141-17/+73
* Merge branch 'wip/i965-separate-sampler-tex' into vulkanJason Ekstrand2015-11-1416-74/+181
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| * i965/vec4: Plumb separate surfaces and samplers through from NIRJason Ekstrand2015-11-143-13/+30
| * i965/vec4: Separate the sampler from the surface in generate_texJason Ekstrand2015-11-141-5/+13
| * i965/fs: Plumb separate surfaces and samplers through from NIRJason Ekstrand2015-11-146-36/+60
| * i965/fs: Separate the sampler from the surface in generate_texJason Ekstrand2015-11-142-6/+15
| * nir: Separate texture from sampler in nir_tex_instrJason Ekstrand2015-11-148-17/+66
* | Merge remote-tracking branch 'mesa-public/master' into vulkanJason Ekstrand2015-11-14328-4365/+8838
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| * nouveau: don't expose HEVC decoding supportIlia Mirkin2015-11-141-0/+1
| * nir: Silence GCC maybe-uninitialized warnings.Vinson Lee2015-11-131-0/+3
| * i965: Add a SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT opcode.Kenneth Graunke2015-11-134-5/+10
| * glsl: Allow implicit int -> uint conversions for the % operator.Kenneth Graunke2015-11-131-9/+28
| * i965: Print input/output VUE maps on INTEL_DEBUG=vs, gs.Kenneth Graunke2015-11-134-1/+40
| * i965: Make convert_attr_sources_to_hw_regs handle stride == 0.Kenneth Graunke2015-11-131-1/+2
| * nir: Add helpers for getting input/output intrinsic sources.Kenneth Graunke2015-11-132-0/+45
| * nir: Don't lower TCS outputs to temporaries.Kenneth Graunke2015-11-131-0/+3
| * nir: Allow outputs reads and add the relevant intrinsics.Kenneth Graunke2015-11-134-8/+21
| * nir/lower_io: Introduce nir_store_per_vertex_output intrinsics.Kenneth Graunke2015-11-133-5/+26
| * nir/lower_io: Use load_per_vertex_input intrinsics for TCS and TES.Kenneth Graunke2015-11-131-4/+8
| * i965: Silence unused parameter warnings in get_buffer_rectIan Romanick2015-11-131-4/+3
| * meta/generate_mipmap: Don't leak the sampler objectIan Romanick2015-11-131-0/+2
| * i965: Remove unneeded #includes.Matt Turner2015-11-131-4/+0
| * i965: Silence warning.Matt Turner2015-11-131-2/+2
| * i965: Don't write beyond allocated memory.Juha-Pekka Heikkila2015-11-131-1/+1
| * i965: Use BRW_MRF_COMPR4 macro in more places.Matt Turner2015-11-134-6/+6
| * i965: Combine register file field.Matt Turner2015-11-137-34/+27
| * i965: Replace HW_REG with ARF/FIXED_GRF.Matt Turner2015-11-1313-211/+157
| * i965/fs: Set stride correctly for immediates in fs_reg(brw_reg).Matt Turner2015-11-131-0/+6
| * i965/fs: Handle type-V immediates in brw_reg_from_fs_reg().Matt Turner2015-11-131-0/+3
| * i965: Rename GRF to VGRF.Matt Turner2015-11-1330-194/+194
| * i965: Move BAD_FILE from the beginning of enum register_file.Matt Turner2015-11-131-1/+1
| * i965: Initialize registers.Matt Turner2015-11-133-2/+18
| * i965: Use brw_reg's nr field to store register number.Matt Turner2015-11-1325-290/+276
| * i965: Unwrap some lines.Matt Turner2015-11-134-12/+4
| * i965/vec4: Remove swizzle/writemask fields from src/dst_reg.Matt Turner2015-11-132-8/+1
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