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* t_dd_dmatmp: Use addition instead of subtraction in loop boundsIan Romanick2015-09-231-1/+1
* t_dd_dmatmp: Pull out common 'count -= count & 3' codeIan Romanick2015-09-231-9/+6
* t_dd_dmatmp: Use '& 3' instead of '% 4' everywhereIan Romanick2015-09-231-2/+2
* t_dd_dmatmp: Clean up improper code formatting from previous patchIan Romanick2015-09-231-12/+6
* t_dd_dmatmp: Make "count" actually be the countIan Romanick2015-09-233-75/+75
* i965/vec4: Don't coalesce regs in Gen6 MATH ops if reswizzle/writemask neededAntia Puentes2015-09-232-3/+12
* mesa: Fix GL_FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE for default framebuffer.Iago Toral Quiroga2015-09-231-1/+10
* glsl: bail out early in _mesa_ShaderSource if no shaderobjTapani Pälli2015-09-231-11/+9
* i965/vec4: Detect and delete useless MOVs.Matt Turner2015-09-221-0/+22
* prog_to_nir: Use nir_op_dphJason Ekstrand2015-09-221-2/+1
* nir/lower_alu_to_scalar: Add support for nir_op_fdphJason Ekstrand2015-09-221-0/+18
* i965/vec4: Add support for fdph_replicatedJason Ekstrand2015-09-221-0/+5
* nir: Add fdph and fdph_replicated opcodesJason Ekstrand2015-09-223-1/+8
* nir/lower_alu_to_scalar: Return after lower_reductionJason Ekstrand2015-09-221-1/+1
* nir/lower_alu_to_scalar: Use the builderJason Ekstrand2015-09-221-25/+22
* i965: Add defines for tessellation stagesChris Forbes2015-09-221-0/+72
* r600g: update num_dw in scissor_enable workaroundGrazvydas Ignotas2015-09-231-0/+1
* i965/vec4: refactor brw_vec4_copy_propagation.Alejandro Piñeiro2015-09-221-14/+18
* st/mesa: remove st_bind_framebuffer()Brian Paul2015-09-221-12/+0
* mesa: const-qualify _mesa_is_legal_tex_storage_format ctx paramBrian Paul2015-09-222-2/+4
* mesa: const-qualify _mesa_base_tex_format() ctx paramBrian Paul2015-09-222-2/+2
* mesa: const-qualify buffer_object_subdata_range_good() bufObj parameterBrian Paul2015-09-221-1/+1
* mesa: whitespace, comment fixes in texstorage.cBrian Paul2015-09-221-15/+18
* mesa/es3.1: Enable GL_ARB_vertex_attrib_binding functionality for GLES 3.1Marta Lofstedt2015-09-221-7/+7
* mesa/es3.1: Allow query of Vertex bindings for GLES 3.1Marta Lofstedt2015-09-221-3/+4
* mesa/es3.1 : Align OpenGL ES 3.1 glBindVertexBuffer error handling with OpenG...Marta Lofstedt2015-09-221-1/+1
* i965: fix textureGrad for cubemapsTapani Pälli2015-09-221-19/+182
* nir: Report progress from nir_normalize_cubemap_coords().Kenneth Graunke2015-09-212-8/+23
* nir: Add braces around multi-line loop.Kenneth Graunke2015-09-211-1/+2
* nir: Report progress from nir_lower_system_values().Kenneth Graunke2015-09-212-10/+19
* nir: Report progress from nir_split_var_copies().Kenneth Graunke2015-09-212-4/+13
* nir: Report progress from nir_lower_locals_to_regs().Kenneth Graunke2015-09-212-4/+16
* nir: Report progress from nir_remove_dead_variables().Kenneth Graunke2015-09-212-5/+12
* nir: Report progress from lower_vec_to_movs().Jason Ekstrand2015-09-212-7/+22
* nir: Report progress from nir_lower_globals_vars_to_local().Kenneth Graunke2015-09-212-2/+6
* i965: Clean up GLSL compiler option setupJason Ekstrand2015-09-211-26/+20
* i965/skl: Use larger URB size where available.Ben Widawsky2015-09-211-1/+2
* nir/builder: Don't use designated initializersJason Ekstrand2015-09-211-3/+18
* nir: Move system value -> intrinsic mapping into nir.cJason Ekstrand2015-09-213-40/+40
* nir: rename nir_lower_samplers.c{pp,}Emil Velikov2015-09-212-5/+3
* nir: add C wrapper around glsl_type::record_location_offsetEmil Velikov2015-09-212-0/+9
* nir: move stdio.h inclusion before extern CEmil Velikov2015-09-211-2/+2
* i965: Fix MRF register number assertions for compr4.Kenneth Graunke2015-09-211-2/+2
* radeonsi: implement TXQS supportIlia Mirkin2015-09-212-25/+69
* radeonsi: load fmask ptr relative to the resources arrayIlia Mirkin2015-09-211-1/+1
* i965/vec4: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+6
* i965/fs: Use MRF registers 21-23 for spilling in gen6Iago Toral Quiroga2015-09-211-4/+7
* i965: Turn BRW_MAX_MRF into a macro that accepts a hardware generationIago Toral Quiroga2015-09-218-28/+28
* i965: Move MRF register asserts out of brw_reg.hIago Toral Quiroga2015-09-214-7/+16
* i965: Maximum allowed size of SEND messages is 15 (4 bits)Iago Toral Quiroga2015-09-214-2/+10
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