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* i965/gen6/gs: Add an additional parameter to the FF_SYNC opcode.Samuel Iglesias Gonsalvez2014-09-194-8/+19
| | | | | | | | | We will use this parameter in later patches to provide information relevant to transform feedback that needs to be set as part of the FF_SYNC message. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_FF_SYNC_SET_PRIMITIVES opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+46
| | | | | | | | | This opcode will be used when filling FF_SYNC header before emitting vertices and their data. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_SVB_SET_DST_INDEX opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+33
| | | | | | | | | This opcode generates code to copy the specified destination index into subregister 5 of the MRF message header. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: implement GS_OPCODE_SVB_WRITE opcodeSamuel Iglesias Gonsalvez2014-09-194-0/+63
| | | | | | | | | This opcode will be used when sending SVB WRITE messages to save transform feedback outputs into Streamed Vertex Buffers. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Enable texture units and upload sampler state.Iago Toral Quiroga2014-09-193-2/+3
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Assign geometry shader VUE map properly.Iago Toral Quiroga2014-09-192-7/+7
| | | | | | | | | | So far in gen6 we only used geometry shaders to implement transform feedback in vertex shaders, so we assumed that the VUE map for the geometry shader stage was always the same as for the vertex shader stage. This is no longer true now that we support user provided geometry shaders in gen6 too. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement support for gl_PrimitiveIdIn.Iago Toral Quiroga2014-09-192-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | For this we will need to move PrimitiveID information, delivered in the thread payload in r0.1, to a separate register (we use GS_OPCODE_SET_PRIMITIVE_ID for this), then map the corresponding varying slot to that register in the setup_payload() method. Notice that we cannot use a virtual register as the destination for the PrimitiveID because we need to map all input attributes to hardware registers in setup_payload(), which happens before virtual registers are mapped to hardware registers. We could work around that issue if we were able to compute the first non-payload register in emit_prolog() and move the PrimitiveID information to that register, but we can't because at that point we still don't know the final number uniforms that will be included in the payload. So, what we do is to place PrimitiveID information in r1, which is always delivered as part of the payload but its only populated with data relevant for transform feedback when we set GEN6_GS_SVBI_PAYLOAD_ENABLE in the 3DSTATE_GS state packet. When we implement transform feedback, we wil make sure to move the value of r1 to another register before we overwrite it with the PrimitiveID. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_SET_PRIMITIVE_ID.Iago Toral Quiroga2014-09-194-0/+27
| | | | | | | | | | In gen6 the geometry shader payload includes the PrimitiveID information in r0.1. When the shader code uses glPimitiveIdIn we will have to move this to a separate hardware register where we can map this attribute. This opcode takes the selected destination register and moves r0.1 there. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Handle the case where a geometry shader emits no output.Iago Toral Quiroga2014-09-192-122/+118
| | | | | | | | | | | | | | | | | | In gen6 we need to end the thread differently depending on whether we have emitted at least one vertex or not. In case we did, the EOT message must always include the COMPLETE flag or else the GPU hangs. If we have not produced any output, however, we can't use the COMPLETE flag. This would lead us to end the program with an ENDIF opcode, which we want to avoid (and actually is not permitted since it hits an assertion), so instead what we do is that we always request a new VUE handle every time we do an URB WRITE, even for the last vertex we emit. With this we make sure that whether we have emitted at least one vertex or none at all we have to finish the thread without writing to the URB, which works for both cases by setting the COMPLETE and UNUSED flags in the EOT message. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Make sure we complete the last primitive.Iago Toral Quiroga2014-09-191-0/+13
| | | | | | | | | Just in case the GS algorithm does not call EndPrimitive() for the last primitive produced. This is relevant only for non point outputs, since for this we are already setting the PrimEnd flag on each vertex we emit. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement geometry shaders for outputs other than points.Iago Toral Quiroga2014-09-192-7/+67
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Add initial implementation for a gen6 geometry shader visitor.Iago Toral Quiroga2014-09-194-1/+415
| | | | | | | | | | | | Geometry shaders in gen6 are significantly different from gen7+ so it is better to have them implemented in a different file rather than adding gen6 branching paths all over brw_vec4_gs_visitor.cpp. This commit adds an initial implementation that only handles point output, which is the simplest case. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Generalize emit_urb_slot() to emit to any dst_reg.Iago Toral Quiroga2014-09-192-14/+20
| | | | | | | | | | In gen7+ we emit vertices as they come, however in gen6 geometry shaders we have to buffer vertex data for all vertices and then emit it all in one go at the end. To achieve this we need to generalize emit_urb_slot() to store vertex data in general purpose registers and not only MRF registers. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Provide means to create registers of a given size.Iago Toral Quiroga2014-09-192-0/+15
| | | | | | | Implemented by Ilia Mirkin <[email protected]>. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_SET_DWORD_2.Iago Toral Quiroga2014-09-195-16/+10
| | | | | | | | | | We had GS_OPCODE_SET_DWORD_2_IMMED but this required its source argument to be an immediate. In gen6 we need to set dword 2 of the URB write message header from values stored in separate register, so we need something more flexible. This change replaces GS_OPCODE_SET_DWORD_2_IMMED with GS_OPCODE_SET_DWORD_2. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Upload binding table for user-provided geometry shaders.Iago Toral Quiroga2014-09-191-1/+4
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Enable URB space for user-provided geometry shaders.Iago Toral Quiroga2014-09-191-10/+20
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Compute URB entry size for user-provided geometry shaders.Iago Toral Quiroga2014-09-192-33/+62
| | | | | Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Add instruction URB flags to geometry shaders EOT message.Iago Toral Quiroga2014-09-191-1/+1
| | | | | | | | | Gen6 seems to require that EOT messages include the complete flag too or else the GPU hangs. We add will this flag to the instruction when we emit the thread end opcode. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_URB_WRITE_ALLOCATE.Iago Toral Quiroga2014-09-195-0/+42
| | | | | | | | | | | Gen6 geometry shaders need to allocate URB handles for each new vertex they emit after the first (the URB handle for the first vertex is obtained via the FF_SYNC message). This opcode adds the URB allocation mechanism to regular URB writes. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gen6/gs: Implement GS_OPCODE_FF_SYNC.Iago Toral Quiroga2014-09-195-0/+67
| | | | | | | | This implements the FF_SYNC message required in gen6 geometry shaders to get the initial URB handle. Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/gs: Reuse gen6 constant push buffers setup code in gen7+.Samuel Iglesias Gonsalvez2014-09-193-36/+7
| | | | | | | | The code required for gen6 and gen7+ is almost the same, so reuse it. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Setup constant push buffers for gen6 geometry shaders.Iago Toral Quiroga2014-09-193-33/+68
| | | | | Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Set brw->gs.enabled to FALSE in gen6_blorp_emit_gs_disable()Samuel Iglesias Gonsalvez2014-09-191-0/+1
| | | | | | | | See 7dfb4b2d00ddb8e5ee24d4c58eb9415dc4ccc21c for more details. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: use brw_gs_prog atom instead of brw_ff_gs_progSamuel Iglesias Gonsalvez2014-09-194-2/+16
| | | | | | | | | | | | | This is needed to support user-provided geometry shaders, since the brw_ff_gs_prog atom in gen6 only takes care of implementing transform feedback for vertex shaders. If there is no user-provided geometry shader the implementation falls back to the original code. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gen6/gs: Skeleton for user GS program supportSamuel Iglesias Gonsalvez2014-09-191-35/+119
| | | | | | | | | | | | | | Currently, gen6 only uses geometry shaders for transform feedback so the state we emit is not suitable to accomodate general purpose, user-provided geometry shaders. This patch paves the way to add these support and the needed 3DSTATE_GS packet modifications for it. Previous code that emitted state to implement transform feedback in gen6 goes to upload_gs_state_adhoc_tf(). Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* i965/gs: Use single dispatch mode as fallback to dual object mode when possible.Iago Toral Quiroga2014-09-194-22/+36
| | | | | | | | | | | | | | | | | | Currently, when a geometry shader can't use dual object mode we fall back to dual instance mode, however, when invocations == 1, single dispatch mode is more performant and equally efficient in terms of register pressure. Single dispatch mode requires that the driver can handle interleaving of input registers, but this is already supported (dual instance mode has the same requirement). However, to take full advantage of single dispatch mode to reduce register pressure we would also need the ability to store two separate vec4 output values into vec8 registers, which would approximately double our capacity to store temporary values, but currently the vec4 visitor and generator classes do not support this, so at the moment register pressure in single and dual instance modes is the same. Reviewed-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]>
* ilo: rename ILO_DEBUG=3dChia-I Wu2014-09-195-6/+6
| | | | | | It has been a bad name since we added the builder. Rename it to ILO_DEBUG=batch to match i965, and call ilo_builder_decode() from ilo_cp_submit_internal().
* ilo: rename ilo_cp_flush()Chia-I Wu2014-09-1911-52/+52
| | | | | | "Flush" is used for too many things already: pipe resource flush, pipe context flush, pipe transfer region flush, and hardware pipeline flush. Rename it to ilo_cp_submit(). As such, ILO_DEBUG=flush is renamed to ILO_DEBUG=submit.
* ilo: remove ilo_cp_empty()Chia-I Wu2014-09-193-22/+12
| | | | Call ilo_builder_batch_used() directly.
* ilo: simplify ilo_cp_set_owner()Chia-I Wu2014-09-195-129/+121
| | | | | | The simplification allows us to get rid of ilo_cp_set_ring() and ilo_cp_implicit_flush(). The 3D query code is refactored for the simplification.
* mesa: Delete VAO _MaxElement code and index buffer bounds checking.Kenneth Graunke2014-09-1915-206/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fredrik's implementation of ARB_vertex_attrib_binding introduced new gl_vertex_attrib_array and gl_vertex_buffer_binding structures, and converted Mesa's older gl_client_array to be derived state. Ultimately, we'd like to drop gl_client_array and use those structures directly. One hitch is that gl_client_array::_MaxElement doesn't correspond to either structure (unlike every other field), so we'd have to figure out where to store it. The _MaxElement computation uses values from both structures, so it doesn't really belong in either place. We could put it in the VAO, but we'd have to pass it around everywhere. It turns out that it's only used when ctx->Const.CheckArrayBounds is set, which is only set by the (rarely used) classic swrast driver. It appears that drivers/x11 used to set it as well, which was intended to avoid segmentation faults on out-of-bounds memory access in the X server (probably for indirect GLX clients). However, ajax deleted that code in 2010 (commit 1ccef926be46dce3b6b5c76e812e2fae4e205ce7). The bounds checking apparently doesn't actually work, either. Non-VBO attributes arbitrarily set _MaxElement to 2 * 1000 * 1000 * 1000. vbo_save_draw and vbo_exec_draw remark /* ??? */ when setting it, and the i965 code contains a comment noting that _MaxElement is often bogus. Given that the code is complex, rarely used, and dubiously functional, it doesn't seem worth maintaining going forward. This patch drops it. This will probably mean the classic swrast driver may begin crashing on out of bounds vertex buffer access in some cases, but I believe that is allowed by OpenGL (and probably happened for non-VBO accesses anyway). There do not appear to be any Piglit regressions, either. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Acked-by: Roland Scheidegger <[email protected]>
* vc4: Add support for stencil operations.Eric Anholt2014-09-188-2/+118
| | | | | | | While depth test state is passed through the fragment shader as sideband, data, the stencil test state has to be set by the fragment shader itself. Many tests are still failing, but this gets most of hiz/ passing.
* vc4: Actually implement VC4_DEBUG=cl.Eric Anholt2014-09-184-0/+141
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* draw: (trivial) remove duplicated linesRoland Scheidegger2014-09-181-12/+0
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* mesa: fix prog_optimize.c assertions triggered by SWZ opcodeBrian Paul2014-09-181-5/+4
| | | | | | | | | | | | | The SWZ instruction can have swizzle terms >4 (SWIZZLE_ZERO, SWIZZLE_ONE). These swizzle terms caused a few assertions to fail. This started happening after the commit "mesa: Actually use the Mesa IR optimizer for ARB programs." when replaying some apitrace files. A new piglit test (tests/asmparsertest/shaders/ARBfp1.0/swz-08.txt) exercises this. Cc: "10.3" <[email protected]> Reviewed-by: Charmaine Lee <[email protected]>
* vc4: Allow copy propagation of uniforms.Eric Anholt2014-09-171-1/+15
| | | | | Fixes 12 piglit tests (and 8 more crash -> fail) from reducing register pressure.
* vc4: Make sure thread end doesn't have a uniform read.Eric Anholt2014-09-171-0/+8
| | | | Prevents regression when I start doing copy propagation on uniforms.
* vc4: Allow dead code elimination of instructions that read uniforms.Eric Anholt2014-09-171-2/+1
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* vc4: Add support for reordering the uniform stream after optimization.Eric Anholt2014-09-174-0/+87
| | | | | | This allows for introducing dead code eliminating of uniforms, copy propagation of uniforms, and instruction rescheduling between instructions that both read uniforms.
* vc4: Initialize the various qreg arrays when allocating them.Eric Anholt2014-09-171-0/+4
| | | | | | | This is particularly important for outputs, where we try to MOV the whole vec4 to the VPM, even if only 1-3 components had been set up. It might also be important for temporaries, if the shader reads components before writing them.
* vc4: Fix stray disable of the CSE pass.Eric Anholt2014-09-171-1/+0
| | | | Somehow I slipped this in with the original commit of CSE.
* gallivm,tgsi: fix idiv by zero crashrconde2014-09-172-7/+25
| | | | | | | | While the result of signed integer division by zero is undefined by glsl (and doesn't exist with d3d10), we must not crash, so need to make sure we don't get sigfpe much like udiv already does. Unlike udiv where we return 0xffffffff (as required by d3d10) there is no requirement right now to return anything specific so we use zero.
* gallivm: add texture target information for sample opcodes to tgsi infoRoland Scheidegger2014-09-171-14/+43
| | | | | | | | | | | | | | sample opcodes don't have valid texture target information (and I don't think this should be changed), however it would be nice if we had that information ready elsewhere, so stuff that information into the tgsi info when analyzing a shader. v2: Ilja Mirkin spotted some bugs wrt not handling msaa resources. So add them and while there also add them to the tex opcode analysis this was cloned from as well (plus get rid of some bug not detecting indirect textures there in some cases too). Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: Fix handling of 8888 SNORM and SRGB formats for big-endianRichard Sandiford2014-09-171-16/+36
| | | | | | | | | | | MESA_FORMAT_x8y8z8w8 puts the x channel in the least significant part of the containing 32-bit integer, which is equivalent to PIPE_FORMAT_xyzw8888. PIPE_FORMAT_x8y8z8w8 puts the x channel first in memory. This patch fixes up the mesa<->gallium mapping accordingly. Signed-off-by: Richard Sandiford <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* st/mesa: Fix handling of LA and RG formats for big-endianRichard Sandiford2014-09-171-16/+48
| | | | | | | | | | | | MESA_FORMAT_LnAn puts the luminance in the least significant part of the containing integer, which is equivalent to PIPE_FORMAT_LAnn. PIPE_FORMAT_LnAn puts the luminance first in memory. This patch fixes up the mesa<->gallium mapping accordingly. Signed-off-by: Richard Sandiford <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: Add MESA_FORMAT_{A8R8G8B8, X8R8G8B8, X8B8G8R8}_SRGB (v2)Richard Sandiford2014-09-179-0/+164
| | | | | | | | | | | | This means that each 8888 SRGB format has a reversed counterpart, which is necessary for handling big-endian mesa<->gallium mappings. v2: fix missing i965 additions. (Jason) fix 127->255 max alpha for SRGB formats. (Jason) v1: Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Richard Sandiford <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: Add MESA_FORMAT_A8L8_{SNORM,SRGB}Richard Sandiford2014-09-179-0/+111
| | | | | | | | | | | | | The associated UNORM format already existed. This means that each LnAn format has a reversed counterpart, which is necessary for handling big-endian mesa<->gallium mappings. [airlied: rebased onto current master] Signed-off-by: Richard Sandiford <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: Define PIPE_FORMAT_xyzw8888_{SNORM, SRGB} aliasesRichard Sandiford2014-09-171-0/+24
| | | | | | | | | ...i.e. formats in which the first listed component is in the least significant byte of the integer. The corresponding UNORM aliases already exist. Signed-off-by: Richard Sandiford <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* gallium: Add PIPE_FORMAT_x8B8G8R8_SNORM formatsRichard Sandiford2014-09-172-0/+6
| | | | | | | | | | | This means that each RnGnBnxn format has a reversed counterpart, which is necessary for handling big-endian mesa<->gallium mappings. The associated UNORM and SRGB formats already exist. Signed-off-by: Richard Sandiford <[email protected]> Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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