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* radeon/llvm: Remove AMDILTargetMachineTom Stellard2012-05-2919-363/+90
* nouveau: unreference fences on resource destructionChristoph Bumiller2012-05-292-0/+6
* nvc0: optimize blend cso by checking which by-RT data actually differsChristoph Bumiller2012-05-291-65/+94
* nvc0: don't upload UCPs if the shader doesn't use themChristoph Bumiller2012-05-291-1/+1
* nvc0/ir: allow 64-bit constant loads on nve4Christoph Bumiller2012-05-292-1/+3
* nvc0/ir: fix texture barrier insertion to prevent WAW hazardsChristoph Bumiller2012-05-296-29/+88
* nvc0/ir: TEX doesn't support JOIN modifier eitherChristoph Bumiller2012-05-291-0/+1
* gallium: add st_api feature mask to prevent advertising MS visualsChristoph Bumiller2012-05-294-12/+37
* nv30: Fix generic passing to fragment program in NV34.Roy Spliet2012-05-253-5/+9
* nv30: handle user index buffersChristoph Bumiller2012-05-254-17/+27
* radeon/llvm: Use a custom inserter for MASK_WRITETom Stellard2012-05-254-34/+36
* radeon/llvm: Use tablegen pattern to lower bitconvertTom Stellard2012-05-254-294/+11
* radeon/llvm: Use a custom inserter to lower FNEGTom Stellard2012-05-255-22/+15
* radeon/llvm: Use a custom inserter to lower CLAMPTom Stellard2012-05-259-84/+41
* radeon/llvm: Use a custom inserter to lower FABSTom Stellard2012-05-2510-42/+41
* r600g: handle R16G16B16_FLOAT and R32G32B32_FLOAT in translate_colorswapKai Wasserbäch2012-05-251-0/+2
* draw: fix primitive restart bug by using the index buffer offsetBrian Paul2012-05-251-3/+6
* svga: remove the special zero-stride vertex array codeBrian Paul2012-05-259-153/+12
* gallium/docs: beef up the docs related to color clampingBrian Paul2012-05-252-3/+18
* util: add GALLIUM_LOG_FILE option for logging output to a fileBrian Paul2012-05-252-6/+25
* i965/msaa: Enable 4x MSAA on Gen7.Paul Berry2012-05-252-9/+9
* i965/msaa: Implement manual blending operation for Gen7.Paul Berry2012-05-251-23/+67
* i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.Paul Berry2012-05-253-68/+151
* i965/msaa: Validate Gen7 surface state constraints.Paul Berry2012-05-253-3/+109
* i965/msaa: Properly handle sliced layout for Gen7.Paul Berry2012-05-2510-58/+162
* i965/msaa: Add defines for Gen7.Paul Berry2012-05-251-0/+5
* i965/blorp: Enable blorp blits on Gen7.Paul Berry2012-05-252-2/+4
* i965/blorp: Implement proper texel fetch messages for Gen7.Paul Berry2012-05-252-2/+31
* i965/blorp: Use 16 pixel dispatch on Gen7.Paul Berry2012-05-251-1/+9
* i965/blorp: Allocate space for push constants on Gen7.Paul Berry2012-05-253-30/+28
* i965/blorp: Set the dynamic state upper bound.Paul Berry2012-05-251-1/+6
* i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.Paul Berry2012-05-253-34/+49
* i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessaryPaul Berry2012-05-254-27/+87
* i965/blorp: Emit sample index in SAMPLE_LD message when necessaryPaul Berry2012-05-252-21/+36
* i965/blorp: Generalize sampling code in preparation for Gen7Paul Berry2012-05-251-26/+61
* i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.Paul Berry2012-05-251-5/+40
* gallium/targets: pass ldflags parameter to MKLIBThomas Gstädtner2012-05-251-1/+1
* Revert "r600g: set round_mode to truncate and get rid of tgsi_f2i on evergreen"Vadim Girlin2012-05-252-6/+56
* radeon/llvm: add FLT_TO_UINT, UINT_TO_FLT instructionsVadim Girlin2012-05-251-0/+20
* radeon/llvm: prepare to revert the round mode state to defaultVadim Girlin2012-05-251-2/+9
* radeon/llvm: fix sampler index in llvm_emit_texVadim Girlin2012-05-251-2/+4
* radeon/llvm: fix opcode for RECIP_UINT_r600Vadim Girlin2012-05-251-1/+1
* radeon/llvm/loader: convert hardcoded gpu name to optionVadim Girlin2012-05-251-2/+3
* r600g: add RECIP_INT, PRED_SETE_INT to r600_bytecode_get_num_operandsVadim Girlin2012-05-251-0/+2
* i915g: Check for geometry shader earlier in i915_set_constant_buffer.Vinson Lee2012-05-241-4/+4
* scons: Fix SCons build infrastructure for FreeBSD.Vinson Lee2012-05-243-3/+3
* radeon/llvm: Lower UDIV using the Selection DAGTom Stellard2012-05-248-212/+126
* radeon/llvm: Remove auto-generated AMDIL->ISA conversion codeTom Stellard2012-05-2414-280/+28
* radeon/llvm: Remove AMDIL instructions MULHI, SMULTom Stellard2012-05-243-10/+5
* radeon/llvm: Remove AMDIL bitshift instructions (SHL, SHR, USHR)Tom Stellard2012-05-248-693/+6
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